Z8018008FSG Zilog, Z8018008FSG Datasheet - Page 34

• Manufacturer Part Number: Z8018008FSG
• Description: IC 8MHZ Z180 CMOS ENH MPU 80-QFP
• Manufacturer: Zilog

Specifications of Z8018008FSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3882; Z8018008FSG

Table 9. Z80180-10 AC Characteristics (continued)
PS014004-1106
No
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
26a
27
28
29
30
31
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol Item
MED1
RDD1
M1D1
AH
MED2
RDD2
M1D2
DRS
DRH
STD1
STD2
WS
WH
WDZ
WRD1
WDD
WDS
WRD2
WRP
WDH
IOD1
IOD2
IOD3
INTS
Ø Fall to MREQ Fall Delay
Ø Fall to RD Fall Delay
Ø Rise to RD Rise Delay
Ø Rise to M1 Fall Delay
Address Hold Time from
(MREQ, IOREQ, RD, WR)
Ø Fall to MREQ Rise Delay
Ø Fall to RD Rise Delay
Ø Rise to M1 Rise Delay
Data Read Set-up Time
Data Read Hold Time
Ø Fall to ST Fall Delay
Ø Fall to ST Rise Delay
WAIT Set-up Time to Ø Fall
WAIT Hold Time from Ø Fall
Ø Rise to Data Float Delay
Ø Rise to WR Fall Delay
Ø Fall to WRITE Data Delay Time
WRITE Data Set-up Time to WR Fall
Ø Fall to WR Rise Delay
WR Pulse Width
WR Pulse Width (I/O WRITE Cycle)
WRITE Data Hold Time from (WR Rise
Ø Fall to IORQ Fall Delay
Ø Rise to IORQ Fall Delay
Ø Fall to IORQ Rise Delay
M1 Fall to IORQ Fall Delay
INT Set-up Time to Ø Fall
IOC = 1
IOC = 0
IOC = 1
IOC = 1
)
Z80180-10
Min
–
–
–
–
10
–
–
–
25
0
–
–
30
30
–
–
–
15
–
110
210
10
–
–
–
200
30
Max
50
50
55
60
–
50
50
60
–
–
60
60
–
–
60
50
60
–
50
–
–
–
50
55
50
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Microprocessor Unit
Architecture
Z80180
28