Z8018008FSG Zilog, Z8018008FSG Datasheet - Page 56

• Manufacturer Part Number: Z8018008FSG
• Description: IC 8MHZ Z180 CMOS ENH MPU 80-QFP
• Manufacturer: Zilog

Specifications of Z8018008FSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3882; Z8018008FSG

ASCI Extension Control Register Channels 0 and 1
PS014004-1106
ASEXT0 and ASEXT1
Note:
TIF1: Timer Interrupt Flag 1 (bit 7)—When
and, when enabled by
is read and the higher or lower byte of
TIF0: Timer Interrupt Flag 0 (bit 6)—When
and, when enabled by
is read and the higher or lower byte of
TIE1: Timer Interrupt Enable 1 (bit 5)—When
CPU interrupt request. When
RESET
TOC1, 0: Timer Output Control (bits 3, 2)—
control the output of
indicated in
register is
programming
when
Table 14. Timer Output Control
TDE1, 0: Timer Down Count Enable (bits 1, 0)—
down counting for
counting is stopped and
during
The ASCI Extension Control Register controls functions newly added to the ASCIs in the
Z80180 family.
TOC1
0
0
1
1
TMDR1
,
RESET
TIE0
All bits in this register reset to 0.
TOC0
0
1
0
1
1
, the
Table
is cleared to
TOC1
decrements to
and
T
Output
Inhibited
Toggled
0
1
OUT
14. During
TMDR1
TMDRn
and
PRT1
TIE1 = 1
TIE0 = 1
function is selected. By
TMDRn
TOC0
0
using the multiplexed
.
and
do not decrement until
If bit 3 of IAR1B is 1, the T
0
The T
PRT.
toggles or is set Low or High as indicated.
TIE0
RESET
.
, an interrupt request is generated.
, an interrupt request is generated
, the
TMDR0
is freely read or written.
OUT
is reset to
T
,
OUT
TOC1
/DREQ pin is not affected by the
TMDR1
TMDR0
, respectively. When
/
DREQ
and
0
, the interrupt request is inhibited. During
is read. During
is read. During
pin can be forced High, Low, or toggled
TOC0
TMDR1
TMDR0
T
TOC1
TDEn
OUT
TIE0
/
are cleared to
DREQ
OUT
TDE1
and
is set to
decrements to
decrements to
TDE1
is set to
/DREQ pin
TDEn
TOC0
pin as
and
RESET
RESET
and
TIF0
TIF1
1
1
.
(
TDE0
,
N = 0,1
TDE0
Microprocessor Unit
TIF1 = 1
0
is reset to
is reset to
,
,
. If bit
TIF1
TIF0
0
0
enable and disable
,
,
) is set to
are cleared to
TIF1
TIF0
is cleared to
is cleared to
generates a
3
of the
is set to
is set to
0
0
Architecture
when
when
1
Z80180
, down
IAR1B
TCR
TCR
1
1
0
0
0
,
,
.
.
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