Z8018008FSG Zilog, Z8018008FSG Datasheet - Page 48

• Manufacturer Part Number: Z8018008FSG
• Description: IC 8MHZ Z180 CMOS ENH MPU 80-QFP
• Manufacturer: Zilog

Specifications of Z8018008FSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3882; Z8018008FSG

PS014004-1106
MPE
error flags.
RE: Receiver Enable (bit 6)—
TE
interrupted. However, the
TE
TE: Transmitter Enable (bit 5)—
TE
interrupted. However, the
TE
RTS0: Request to Send Channel 0 (bit 4 in CNTLA0 only)—
Configuration Register is
ASCI to control (
by connecting to that device’s
side effects on other ASCI registers or flags. Bit
MPBR/EFR: Multiprocessor Bit Receive/Error Flag Reset (bit 3)—
mode is enabled (
the most recent receive operation. When written to
error flags (
during
MOD2, 1, 0: ASCI Data Format Mode 2, 1, 0 (bits 2–0)—
data format as listed in
Table 10. ASCI Data Formats Mode 2, 1, 0
The data formats available based on all combinations of
indicated in
Bit
MOD2 = 0
MOD2 = 1
MOD1 = 0
MOD1 = 1
MOD0 = 0
MOD0 = 1
is reset to
is cleared to
is reset to
is cleared to
is reset to
RESET
MPE
OVRN
Table
0
0
.
, the transmitter is disables and any transmit operation in progress is
, the transmitter is disabled and any transmit operation in progress is
Description
0→7 bit data
1→8 bit data
0→No parity
1→Parity enabled
0→1 stop bit
1→2 stop bits
0
0
0
, all bytes, regardless of the state of the
is cleared to
START/STOP
MP
in
in
,
11.
FE
IOSTOP
IOSTOP
in
,
PE
Table
CNTLB = 1
TDRE
TDRE
0
and
, the
mode during
mode during
10.
0
CTS
) another communication devices transmission (for example,
BRK
When
during
RTS0/TxS
flag is not reset and the previous contents of
flag is not reset and the previous contents of
When
),
input).
in the
MPBR
RE
RESET
TE
is set to
RESET
RESET
pin features the
RTS0
ASEXT
, when read, contains the value of the
is set to
.
is essentially a
4
.
.
1
in
register) to
, the ASCI transmitter is enabled. When
0
, the
1
CNTLA1
, the ASCI receiver is enabled. When
MPB
MOD2
EFR
RTS0
These bits program the ASCI
function is selected to reset all
data bit, affect the
0
is not used.
.
,
If bit
1
function.
MPBR/EFR
MOD1
bit output port, having no
Microprocessor Unit
4
When multiprocessor
of the System
, and
RTS0
is undefined
MOD0
TDRE
TDRE
allows the
Architecture
MPB
REDR
are held.
are held.
are
Z80180
bit for
and
42