MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 194

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

CPU32+
taken prior to restarting the instruction. If the exception handler does not alter the stacked
SR trace bits, the trace is requeued when the instruction is started.
The breakpoint pending bits are stacked in the SSW, even though the instruction is restarted
upon return from the handler. This avoids problems with bus state analyzer equipment that
has been programmed to breakpoint only the first access to a specific location or to count
accesses to that location. If this response is not desired, the exception handler can clear the
bits before return. The RM, IN, RW, SZCx, FUNC, and SIZ fields reflect the type of bus cycle
that caused the fault. If the bus cycle was an RMW, the RM bit will be set, and the RW bit
will show whether the fault was on a read or write.
5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer. Bus faults that occur as a
result of MOVEM operand transfer are classified as type III faults. MOVEM instruction
prefetch faults are type II faults.
Type III faults cause an immediate exception that aborts the current instruction. Registers
altered during execution of the faulted instruction are not restored prior to execution of the
fault handler. This includes any register predecremented as a result of the effective address
calculation or any register overwritten during instruction execution. Since postincremented
registers are not updated until the end of an instruction, the register retains its pre-instruction
value unless overwritten by operand movement.
The SSW for faults in this category contains the following bit pattern:
MV is set, indicating that MOVEM should be continued from the point where the fault
occurred upon return from the exception handler. TR, B1, and B0 are set if a corresponding
exception is pending when the bus error exception is taken. IN is set if a bus fault occurs
while prefetching an opcode or an extension word during instruction restart. RW, SZCx, SIZ,
and FUNC all reflect the type of bus cycle that caused the fault. All write faults have the RR
bit set to indicate that the write should be rerun upon return from the exception handler.
The remainder of the stack frame contains sufficient information to continue MOVEM with
operand transfer following a faulted transfer. The address of the next operand to be trans-
ferred, incremented or decremented by operand size, is stored in the faulted address loca-
tion ($08). The stacked transfer counter is set to 16 minus the number of transfers attempted
(including the faulted cycle). Refer to Figure 5-12 for the stacking format.
5.5.3.1.4 Type IV—Faults During Exception Processing. The fourth type of fault occurs
during exception processing. If this exception is a second address or bus error, the machine
halts in the double bus fault condition. However, if the exception is one that causes a four-
or six-word stack frame to be written, a bus cycle fault frame is written below the faulted
exception stack frame.
5-52
15
0
14
1
SZC1
13
TR
12
11
B1
Freescale Semiconductor, Inc.
For More Information On This Product,
B0
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
RR
9
8
0
IN
7
RW
6
SZC0
5
4
SIZ
3
2
MOTOROLA
FUNC
0