MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 736

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

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The next step is to configure the system RAM. The address space for the RAM should
include the address of the stack pointer initialized during reset. (One other option would be
to point the stack pointer into the QUICC internal RAM; however, this internal RAM will prob-
ably be used later for serial channel buffer descriptors. Therefore, this idea is recommended
only for the initial phases of debugging. (See step 3 discussed earlier.)
Once the system RAM is initialized, it should be tested by the user to see if it exists at all
intended addresses.
Step 13: Copy the EVT to System RAM
The exception vector table (EVT) can be copied to system RAM at this time to allow greater
flexibility in choosing and modifying the exception vector values. Most embedded operating
systems require the EVT to be located in RAM. Once the table is copied, the VBR should be
modified to point to the beginning of the exception vector table in system RAM, rather than
pointing to ROM.
Step 14: Initialize All Other Memory and Peripherals
Initialize the remaining CSx and DRAM RASx pins in the memory controller. Then test
access to each memory and peripheral in the system.
If DRAM is used, wait the appropriate time after power-up (usually around 100 s) before
accessing the DRAM. Before writing the DRAM, the user normally must make the required
number of read accesses (usually eight) to the DRAM using the CPU or must wait for the
DRAM refresh controller to complete that number of refreshes. Other initialization activity
can proceed while waiting for the DRAM.
Step 15: Initialize the Rest of the SIM60
The next step is to finish initializing the SIM60 as desired. In particular, the module configu-
ration register (MCR) has a number of "fine-tuning" choices that should be initialized.
Step 16: Generate a SIM60 Interrupt
The next step is to try an interrupt source. The simplest interrupt source on the QUICC to try
is the periodic interrupt timer (PIT). It is completely controlled in software.
To prepare for this interrupt, initialize the PIT registers, but leave the timer disabled until
everything else is ready.
First, write the PIRQL0–PIRQL2 bits in the PICR with the desired interrupt level. Suggestion:
choose interrupt level 1. Do not use level 7 for this interrupt, at least during initial stages of
debugging. Then write the PIV bits in the PICR to determine the vector. Example: write $40
(64 decimal) to choose the first user-defined vector in the exception vector table.
Next, using the VBR value written in a previous step, write the address of the interrupt han-
dler into the appropriate vector offset of the exception vector table. For instance, for vector
number $40 and the VBR pointing to $800000, the interrupt handler address is written to
$80000100. (The vector number is multiplied by 4 to obtain the offset.)
9-16
MC68360 USER’S MANUAL
MOTOROLA
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