MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 195

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The SSW for a fault within an exception contains the following bit pattern:
TR, B1, and B0 are set if a corresponding exception is pending when the bus error exception
is taken.
The contents of the faulted exception stack frame are included in the bus fault stack frame.
The pre-exception SR and the format/vector word of the faulted frame are stacked. The type
of exception can be determined from the format/vector word. If the faulted exception stack
frame contains six words, the PC of the instruction that caused the initial exception is also
stacked. This data is placed on the stack in the format shown in Figure 5-13. The return
address from the initial exception is stacked for RTE .
5.5.3.2 CORRECTING A FAULT. There are two ways to complete a faulted released write
bus cycle. The first is to use a software handler. The second is to rerun the bus cycle via
RTE.
Type II fault handlers must terminate with RTE, but specific requirements must also be met
before an instruction is restarted.
There are three varieties of type III operand fault recovery. The first is completion of an
instruction in software. The second is conversion to type II with restart via RTE. The third is
continuation from the fault via RTE.
5.5.3.2.1 Type I—Completing Released Writes via Software. To complete a bus cycle in
software, a handler must first read the SSW function code field to determine the appropriate
address space, access the fault address pointer on the stack, and then transfer data from
the stacked image of the output buffer to the fault address.
If the CPU32+ is configured to 16-bit operation, rather than 32-bit operation, on the internal
data bus, long operands require two bus accesses. A fault during the second access of a
long operand causes the SZCx bits in the SSW to be set to long word. The SIZ field indicates
remaining operand size. If operand coherency is important, the complete operand must be
rewritten. After a long operand is rewritten, the RR bit must be cleared. Failure to clear the
RR bit can cause the RTE instruction to rerun the bus cycle. Following rewrite, it is not nec-
essary to adjust the PC (or other stack contents) before executing RTE.
5.5.3.2.2 Type I—Completing Released Writes via RTE. An exception handler can use
the RTE instruction to complete a faulted bus cycle. When RTE executes, the fault address,
data output buffer, PC, and SR are restored from the stack. Any pending breakpoint or trace
exceptions, as indicated by TR, B1, and B0 in the stacked SSW, are requeued during SSW
restoration. The RR bit in the SSW is checked during the unstacking operation; if it is set,
the RW, FUNC, and SIZ fields are restored and the released write cycle is rerun.
To maintain long-word operand coherence, stack contents must be adjusted prior to the
RTE execution. The fault address must be decremented by 2 if the SZCx bits are set to long
MOTOROLA
15
1
14
0
SZC1
13
TR
12
Freescale Semiconductor, Inc.
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B1
For More Information On This Product,
B0
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
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0
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SZC0
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SIZ
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FUNC
CPU32+
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