MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 614

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Management Controllers (SMCs)
7.11.7.15 SMC UART MASK REGISTER (SMCM). The SMCM is referred to as the SMC
UART mask register when the SMC is operating as a UART. It is an 8-bit read-write register
with the same bit format as the SMC UART event register. If a bit in the SMC UART mask
register is a one, the corresponding interrupt in the event register will be enabled. If the bit
is zero, the corresponding interrupt in the event register will be masked. This register is
cleared upon reset.
7.11.8 SMC UART Example
The following list is an initialization sequence for 9600 baud, 8 data bits, no parity, and 1 stop
bit operation of an SMC UART assuming a 25-MHz system frequency. BRG1 and SMC1 are
used.
7-290
1. The SDCR (SDMA configuration register) should be initialized to $0740, rather than
2. Configure the port B pins to enable the SMTXD1 and SMRXD1. Write PBPAR bits
3. Configure the BRG1. Write BRGC1 with $010144. The DIV16 bit is not used, and
4. Connect the BRG1 clock to SMC1 using the SI. Write the SMC1 bit in SIMODE with
5. Write RBASE and TBASE in the SMC parameter RAM to point to the Rx BD and Tx
6. Program the CR to execute the INIT RX & TX PARAMS command for this channel.
7. Write RFCR with $18 and TFCR with $18 for normal operation.
8. Write MRBLR with the maximum number of bytes per receive buffer. For this case,
9. Write MAX_IDL with $0000 in the SMC UART-specific parameter RAM to disable
10. Clear BRKLN and BRKEC in the SMC UART-specific parameter RAM for the sake
11. Set BRKCR to $0001, so that if a STOP TRANSMIT command is issued, one break
12. Initialize the Rx BD. Assume the Rx data buffer is at $00001000 in main memory.
13. Initialize the Tx BD. Assume the Tx data buffer is at $00002000 in main memory
being left at its default value of $0000.
6 and 7 with ones. Write PBDIR bits 6 and 7 with zeros. Write PBODR bits 6 and 7
with zeros.
the divider is 162 (decimal). The resulting BRG1 clock is 16x the desired bit rate
of the UART.
a 0. Write the SMC1CS bits in SIMODE with 000.
BD in the dual-port RAM. Assuming one Rx BD at the beginning of dual-port RAM
and one Tx BD following that Rx BD, write RBASE with $0000 and TBASE with
$0008.
For instance, to execute this command for SCC1, write $0001 to the CR. This com-
mand causes the RBPTR and TBPTR parameters of the serial channel to be updated
with the new values just programmed into RBASE and TBASE.
assume 16 bytes, so MRBLR = $0010.
the MAX_IDL functionality for this example.
of clarity.
character will be sent.
Write $B000 to Rx_BD_Status. Write $0000 to Rx_BD_Length (not required—done
for instructional purposes only). Write $00001000 to Rx_BD_Pointer.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
MOTOROLA