MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 493

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

7.10.16.22 S-RECORDS PROGRAMMING EXAMPLE. In the following paragraphs, an
example of a downloading application is given that utilizes an SCC channel as a UART con-
troller. The application performs downloads and uploads of S-records between a host com-
puter and an intelligent peripheral through a serial asynchronous line.;
The S-records are strings of ASCII characters that begin with ‘S’ and end in an end-of-line
character. This characteristic will be used to impose a message structure on the communi-
cation between the devices. Note that each device may also transmit XON and XOFF char-
acters for flow control, which do not form part of the program being uploaded or downloaded.
The UART mode register should be set as required, with the FRZ bit cleared and the ENT
and ENR bits set. Receive buffers should be linked to the receive buffer table with the inter-
rupt (I) bit set. For simplicity, assume that the line is not multidrop (no addresses are trans-
mitted) and that each S-record will fit into a single data buffer.
Three characters should first be entered into the UART control character table:
To receive the S-records, the CPU32+ core must only wait for the RX interrupt, indicating
the reception of a complete S-record buffer. Transmission requires assembling S-records
into data buffers and linking them to the transmit buffer table (transmission may be tempo-
rarily halted by reception of an XOFF character). This scheme minimizes the number of
interrupts received by the CPU32+ core (one per S-record) and relieves it from the task of
continually scanning for control characters.
7.10.17 HDLC Controller
Layer 2 of the seven-layer OSI model is the data link layer. One of the most common layer
2 protocols is HDLC. In fact, many other common layer 2 protocols are heavily based on
MOTOROLA
1. Line Feed—Both the E and R bits should be cleared. When an end-of-line character
2. XOFF—E should be cleared, and R should be set. Whenever the CPU32+ core re-
3. XON—XON should be received after XOFF. E should be cleared, and R should be set.
is received, the current buffer is closed (the next BD taken by the CP) and made avail-
able to the CPU32+ core for processing. This buffer contains an entire S record, which
the processor can now check and copy to memory or disk as required.
ceives a control character received interrupt and the receive control character register
contains XOFF, the software should immediately stop transmitting to the other station
by setting the FRZ bit in the UART mode register. This prevents data from being lost
by the other station when it runs out of receive buffers.
The FRZ bit on the transmitter should now be cleared. The CP automatically resumes
transmission of the serial line at the point at which it was previously stopped. Like
XOFF, the XON character is not stored in the receive buffer.
After 16 bytes have been transmitted, the Tx BD is closed. Ad-
ditionally, the receive buffer is closed after 16 bytes have been
received. Any additional receive data beyond 16 bytes will cause
a busy (out-of-buffers) condition since only one Rx BD was pre-
pared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Serial Communication Controllers (SCCs)
7-169