MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 740

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Applications
9.3.4.1.2 System Control Register (SCR). The functions of this register are found in vari-
ous places in the QUICC.
9-20
may be simultaneously set. If CFC is zero, leave AS7–AS0 as zeros.
LPCD, LPEN, LPP16, and LPREC bits implement low-power functions in the MC68302.
The QUICC allows full operation at low speeds (due to its static design), as well as a num-
ber of enhanced power reduction options and a special low-power stop instruction (LP-
STOP). The user should reference Section 6 System Integration Module (SIM60) for full
details.
The HWDCN2–HWDCN0, HWDEN, and HWT bits are used to control and derive status
from the MC68302 hardware watchdog. This function, called the bus monitor on the
QUICC, is part of the SIM60. See the BME and BMT1–BMT0 bits in the system protection
control register (SYPCR).
The SAM bit is used to control external masters that access the MC68302. This function
is controlled in the SIM60 by the BSTM bit in the module configuration register (MCR).
The FRZ2–FRZ1 and FRZW bits control freeze operation. In the QUICC, more freeze op-
tions are available. See the freeze bits in the MCR of the SIM60, the SDMA configuration
register (SDCR), timer global configuration register (TGCR), and the IDMA channel con-
figuration register (ICCR) of the CPM.
The BCLM bit and IPA bits are used to allow the M68000 core to give all interrupts higher
priority than external bus masters. In the QUICC, this function can be refined to just a
range of interrupt levels. See the BCLRISM2–BCLRISM0 bits in the MCR.
The ADCE and ADC bits determine the result (such as a BERR assertion) of an overlap
in the chip select ranges. This function is not available on the QUICC.
The EMWS bit adds an additional wait state for external masters that are accessing the
MC68302 in a synchronous fashion and adds a wait state when external masters use
MC68302 chip selects. This function is implemented in the DW40 and EMWS bits of the
global memory register (GMR) in the QUICC memory controller.
The RMCST bit determines the M68000 bus functionality during the TAS instruction and
gives the option of exact MC68000-bus compatibility on the MC68302. On the QUICC,
this function is not required since an M68030-type bus is used.
The MC68302 WPVE and WPV bits are used to determine the result (such as a BERR
assertion) of a write operation to a read-only chip select. See the WPER bit in the memory
controller status register (MSTAT) for the QUICC definition.
The VGE bit allows the MC68302 to generate vectors for interrupt acknowledge cycles
while in slave mode. With QUICC in slave mode, all internal interrupts generate vectors.
For interrupts using the IRQx pins, this decision is based on the autovector register. Either
a vector is placed on the bus, or the AVECO pin is asserted (which can be ignored).
The ERRE bit is used with the DRAM refresh controller on the MC68302. The QUICC con-
tains a full DRAM controller that does not require the assistance of the RISC controller;
therefore, this bit is not implemented in the QUICC.
The other status bits in this register were already discussed.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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