MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 259

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

If the actual system clock is placed on the EXTAL pin (rather than an external crystal), the
multiplier defaults to 2, giving a 2 VCO output of 2 the EXTAL frequency. The multiplier
bits should not be modified by the user in this case. See 6.5.4 Low-Power Divider for meth-
ods of reducing clock rates.
6.5.3.2 SKEW ELIMINATION. The PLL is capable of eliminating the skew between the
external clock entering the chip (EXTAL) and the internal clock phases. The PLL also elim-
inates the skew between EXTAL and the CLKO2–CLKO1 pins, providing advantages in
generating low-skew clocking outputs.
The skew is less than 2 ns. Without the PLL enabled, the clock skew could be much larger.
This significant reduction of the clock skew is useful for synchronous clocking of multiple
system components. For instance, a 25-MHz QUICC may generate clocks for the
MC68040—both the 25-MHz BCLK (EXTAL) and the 50-MHz PCLK (CLKO2) may be
obtained from a single 25-MHz system clock input to the QUICC.
6.5.4 Low-Power Divider
The output of the PLL is sent to a low-power divider block. This block generates all other
clocks in normal operation, but has the ability to divide the output frequency of the VCO
before it generates the SyncCLK, BRGCLK, and general system clock to the rest of the
QUICC.
The purpose of the low-power divider block is to allow the user to reduce and restore the
operating frequencies of different sections of the QUICC without losing the PLL lock. Using
the low-power divider block, the user can still obtain full chip operation, but at a slower fre-
quency. This configuration is called slow-go mode. The selection and speed of the slow-go
mode may be changed at any time, with changes occurring immediately.
The low-power divider block is controlled in the CDVCR. The default state of the low-power
divider is to divide all clocks by 1. Thus, for a 25-MHz system, the SyncCLK, BRGCLK, and
general system clock are each 25 MHz.
If the low-power divider block is not used and the user is concerned that errant software
could accidentally write the CDVCR, the user may set a write protection bit in CDVCR to pre-
vent further writes to the register.
6.5.5 QUICC Internal Clock Signals
The internal logic of the QUICC uses five internal clock lines: general system clock, BRG-
CLK, SyncCLK, SIMCLK, and SPCLK. The QUICC also generates two external clock lines
MOTOROLA
If the PLL is used, the resulting 2 VCO output should be a min-
imum of 20 MHz, meaning that the minimum QUICC system fre-
quency should be 10 MHz (i.e., EXTAL
Use the clock divider control register (CDVCR) to divide the sys-
tem clock by more than 1 if fully functional operation at less than
10 MHz is desired.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
(MF + 1) >= 10 MHz.)
System Integration Module (SIM60)
6-15