MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 452

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
Although TBPTR need never be written by the user in most applications, it may be modified
by the user when the transmitter is disabled or when the user is sure that no transmit buffer
is currently in use (e.g., after STOP TRANSMIT command is issued, or after a GRACEFUL
STOP TRANSMIT command is issued, and the frame completes its transmission.)
7.10.7.6 OTHER GENERAL PARAMETERS. Additional parameters are listed in Table 7-5.
These parameters do not need to be accessed by the user in normal operation, and are
listed only because they may provide helpful information for experienced users and for
debugging.
The Rx and Tx internal data pointers are updated by the SDMA channels to show the next
address in the buffer to be accessed.
The Tx internal byte count is a down-count value that is initialized with the Tx BD data length
and decremented with every byte read by the SDMA channels. The Rx internal byte count
is a down-count value that is initialized with the MRBLR value and decremented with every
byte written by the SDMA channels.
The Rx internal state, Tx internal state, Rx temp, Tx temp, and reserved areas are for RISC
use only.
7.10.8 Interrupts from the SCCs
Interrupt handling for each of the SCC channels is configured on a global (per channel) basis
in the CPM interrupt pending register, CPM interrupt mask register, and CPM in service reg-
ister. Within each of these registers, one bit is used to either mask, enable, or report the
presence of an interrupt in an SCC channel. The interrupt priority between the four SCCs is
programmable in the CP interrupt configuration register. An SCC interrupt may be caused
by a number of events. To allow interrupt handling for these (SCC-specific) events, further
event registers are provided within the SCCs.
A number of events can cause the SCC to interrupt the processor. The events differ slightly
according to the protocol selected. For a detailed description of the events see the specific
protocol paragraphs. These events are handled independently for each channel by the SCC
event register and the SCC mask register.
Events that can cause interrupts due to the CTS and CD modem lines are described in
7.14.9 Port C Pin Functions.
7.10.8.1 SCC EVENT REGISTER (SCCE). The 16-bit SCC event register is used to report
events recognized by any of the SCCs. On recognition of an event, the SCC will set its cor-
responding bit in the SCC event register (regardless of the corresponding mask bit). The
SCC event register appears to the user as a memory-mapped register and may be read at
any time. A bit is cleared by writing a one (writing a zero does not affect a bit’s value). More
than one bit may be cleared at a time. This register is cleared at reset.
7-128
To extract data from a partially full receive buffer, the CLOSE Rx
BD command may be used.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
MOTOROLA