MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 304

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Integration Module (SIM60)
6.12.1 DRAM Normal Access Support
When accessing a DRAM, the DRAM controller uses the RAS and CAS pins. When an
access to a DRAM memory bank is made, a normal cycle occurs when DSSEL = 1 in the
OR, PGME = 0 in the OR, and BACK40 = 0 in the BR. The timing of the cycle is program-
mable using the TCYC bits in the OR.
A normal DRAM access can also be made by an external MC68EC040. In this case, the
WBT40 bit determines the RAS precharge time, and the TSS40 bit determines how TS is
sampled.
A normal DRAM access can also be made by an external MC68030/QUICC. In this case,
the WBTQ bit determines the RAS precharge time.
The DRAM controller initiates a transaction by driving the row address on the low address
lines. After the value on the address pins is the row address, the DRAM controller asserts
RAS. One clock phase later, the column address is driven on the low address lines as
defined by the programmed DRAM size, and a clock phase later, the CAS signal is asserted.
If the cycle is a write transfer, then data is output at that point. The DRAM controller then
waits for the expiration of the TCYC length attribute and completes the cycle. The next cycle
will begin only after the value programmed in the WBTQ field expires.
The assertion of RAS can be delayed by one clock phase to relax the address to RAS timing
by setting the TRLXQ bit in the BR. When this bit is set the column address is driven one
clock later, and CAS is delayed by one clock (see Figure 6-16).
The DRAM controller may also generate and check four parity lines (PRTY3–PRTY0). The
parity can be either odd or even as programmed with the OPAR bit in the GMR. During write
cycles, the DRAM controller generates the parity on the four parity lines. During a read cycle,
the DRAM controller checks the parity. If the PAREN bit in the BR is set when a parity error
occurs, the DRAM controller asserts the PERR line and sets the PERx bit in the MSTAT.
For internal cycles, the DRAM controller will assert BERR when a parity error occurs and
the PBEE bit in the GMR is set.
6.12.2 DRAM Page Mode Support
The DRAM banks supports a page mode memory access to DRAMs for the internal masters
and for an external QUICC/MC68030-type master. A memory bank is configured to page
mode if its DSSEL and PGME bits in the OR are set.
Many DRAMs support a page mode operation that reduces access time if multiple accesses
are performed within the same page. In this mode, the DRAM controller continues to assert
6-60
Read-modify-write cycles may be performed using the DRAM
controller. These are implemented as a read cycle followed by a
write cycle. Some DRAMs offer a special read-modify-write ac-
cess using special timing. This access timing is not supported by
the QUICC's DRAM controller.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
MOTOROLA