MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 638

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Peripheral Interface (SPI)
7.12.3 SPI Clocking and Pin Functions
The SPI can be configured as a master for the serial channel, meaning that it generates both
the enable and clock signals, or as slave, meaning that the enable and clock signals are
inputs to the SPI. The SPI also supports operation in a multi-master environment.
When the SPI is a master, the SPI baud rate generator is used to generate the SPI transmit
and receive clocks. The SPI baud rate generator takes its input from the BRGCLK.
The BRGCLK is generated in the clock synthesizer of the QUICC specifically for the SPI
baud rate generator and the other four baud rate generators in the CPM. BRGCLK defaults
to the system frequency (25 MHz). However, the clock synthesizer in the SIM60 has an
option to divide the BRGCLK by 1, 4, 16, or 64 before it leaves the clock synthesizer. What-
ever the resulting frequency of BRGCLK, the user may use that BRGCLK frequency as the
input to the SPI baud rate generator.
The ability to reduce the frequency of BRGCLK before it leaves the clock synthesizer is use-
ful for two reasons. First, in a low-power mode, the baud rate generator clocking could be a
significant factor in overall QUICC power consumption. Thus, if none of the QUICC baud
rate generators need to generate high frequencies nor require a high resolution in the user
application, a lower frequency BRGCLK may be input to the baud rate generators. Secondly,
the user may wish to dynamically change the general system clock frequency in the clock
synthesizer (SLOW GO mode), while still having the baud rate generator run at the original
frequency. The BRGCLK allows this option also.
The SPI master-in slave-out (SPIMISO) pin is an input in master mode and an output in
slave mode. The SPI master-out slave-in (SPIMOSI) pin is an output in master mode and
an input in slave mode. The reason the pins names SPIMOSI and SPIMISO change func-
tionality between master and slave mode is to support a multi-master configuration that
allows communication from any SPI to any other SPI with the same hardware configuration.
7-314
• Multi-Master Environment Support
• Continuous Transfer Mode for auto scanning of a peripheral
• Supports Clock Rates up to 6.25 MHz in Master Mode and up to 12.5 MHz in Slave
• Independent Programmable Baud Rate Generator
• Programmable Clock Phase and Polarity
• Open-Drain Output Pins support multi-master configuration
• Local Loopback Capability for Testing
Mode (assuming a 25-MHz system clock)
User should note the maximum clock rate dose not equal maxi-
mum data rate. See Appendix A Serial Performance for more
detail.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
MOTOROLA