MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 429

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Baud Rate Generators (BRGs)
clock for multiple BRGs. The clock signals on the CLK2 and CLK6 pins are not synchronized
internally prior to being used by the BRG.
Next, the BRG provides a divide-by-16 option before the clock reaches the prescaler. This
option is chosen by the DIV16 bit.
The clock is then divided in the prescaler by up to 4096. This input clock divide ratio can be
programmed on the fly. Two on-the-fly BRG changes should not occur within a time shorter
than the period of at least two BRG input clocks.
The output of the prescaler is sent internally to the bank of clocks and may also be output
externally on the BRGOx pins of either the port A or port B parallel I/O. One BRGOx pin
(BRGO4–BRGO1) is an output from the corresponding BRG. If the BRG divides the clock
by an even value, the transitions of the BRGO pin will always occur on the falling edge of
the input clock to the BRG. If the BRG is programmed to an odd value, the transitions will
alternate between the falling and rising edges of the input clock.
Additionally, the output of the BRG may be sent to the autobaud control block described in
the following paragraphs.
7.9.1 Autobaud Support
In the autobaud process, a UART deduces the baud rate of its received character stream by
looking at the pattern received as well as the timing information of that pattern. The QUICC
BRGs have a built-in autobaud control function that automatically measures the length of a
start bit and modifies the baud rate accordingly. (This capability was only available on the
MC68302 with a special microcode option.)
If the ATB bit in the BRG is set, the autobaud control block starts to search for a low level
on the corresponding RXDx input line (RXD4–RXD1). When it finds a low level on the RXDx
line, it assumes that this is the beginning of a start bit and begins counting the start bit length.
During this time, the BRG output clock toggles for 16 BRG clock cycles at the BRG input
clock rate, and then stops with the BRGO output clock in the low state.
After the RXDx line changes back to the high level, the autobaud control block rewrites the
CD and DIV16 bits in the BRG configuration register to the divide ratio it found. Due to mea-
surement error that can occur at high baud rates, this divide rate written by the autobaud
controller may not be the precise, final baud rate desired by the user (e.g., 56600 could be
the resulting baud rate, rather than 57600). Thus, an interrupt is provided to the user in the
UART SCC event register to signify that the BRG configuration register was rewritten by the
autobaud controller. On recognition of this interrupt, the user should rewrite the BRG con-
figuration register with the desired value. The user is encouraged to do this as quickly as
possible, even prior to the first character being fully received, to ensure that all characters
are recognized correctly by the UART. The first data must have a transition from 1 to 0, then
look for a one again. Thus the first cahracter must be an odd character.
Once a full character is received, the user may check in software to see if the received char-
acter matches a predefined value (such as "a" or "A"; it must be an odd character). Software
should then check for other characters (such at "t" or "T") and program the SCC to the
MOTOROLA
MC68360 USER’S MANUAL
7-105
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