MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 694

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

CPM Interrupt Controller (CPIC)
7.15.1 Overview
An overview of the QUICC interrupt structure is shown in Figure 7-99. The upper half of the
figure shows the CPIC. The CPIC receives interrupts from internal sources such as the four
SCCs, the two SMCs, the SPI, the two IDMA controllers, the PIP, the general-purpose tim-
ers, and the port C parallel I/O pins. The CPIC allows masking of each interrupt source.
When multiple events within a CPM sub-block can cause the interrupt, each event is also
maskable in that CPM sub-block.
All CPM sub-block interrupt sources are prioritized, and bits are set in the CPM interrupt
pending register (CIPR). All 28 interrupt sources within the CIPR are assigned one program-
mable priority level (1–7) before the request for an interrupt is sent to the IMB. (On the
MC68302, all interrupt sources are fixed at priority level 4; however, on the QUICC, the inter-
rupt level is programmable to be 1–7.)
Within the CPM interrupt level, the 28 sources are assigned a priority structure. On the
MC68302, the interrupts have a fixed priority structure; however, on the QUICC, some flex-
ibility is given to the user concerning the relative priority of the 28 interrupt sources. This flex-
ibility is in two areas: 1) the ability to modify the relative priority of the SCCs and 2) the ability
to choose any interrupt source to be the highest of the 28 sources.
Once an unmasked interrupt source is pending in the CIPR, the CPIC sends an interrupt
request to the IMB. This request is at level 1, 2, 3, 4, 5, 6, or 7. The CPIC then waits for an
interrupt acknowledge cycle to occur on the bus.
Once an interrupt cycle occurs at the interrupt level that matches the CPIC interrupt request,
an interrupt arbitration begins on the IMB. The interrupt arbitration process is designed to
choose between multiple requests at the same level. For instance, if the CPM request is at
level 4, but an external peripheral is simultaneously requesting service on the IRQ4 pin, an
interrupt arbitration process is required to decide who wins the interrupt. (The interrupt arbi-
tration process does not affect users who can assign all interrupt sources in the system to a
unique interrupt level 1–7.)
In the interrupt arbitration process, the module places its arbitration ID on the IMB. The arbi-
tration ID ranges in value from 0–15. The CPIC arbitration ID is always fixed at 8. The higher
arbitration value always wins.
Assuming that the CPM wins the arbitration process, the CPM places its 8-bit vector on the
bus, corresponding to the sub-block with the highest current priority. The vector is composed
of two parts. The three MSBs of the interrupt vector come from a 3-bit field in the CPM inter-
7-370
The other source of interrupts on the QUICC is the SIM60, which
has a programmable arbitration ID (initially 15). Thus, if a SIM
sub-block is programmed to the same interrupt level, then a
higher SIM60 arbitration ID selects whether the SIM60 has a
higher interrupt priority than the CPM.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
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