MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 204

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

CPU32+
5.6.2.2.1 External BKPT Signal. Once enabled, BDM is initiated whenever assertion of
BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is acknowl-
edged. The BKPT input has the same timing relationship to the data strobe trailing edge as
read cycle data. There is no breakpoint acknowledge bus cycle when BDM is entered.
5.6.2.2.2 BGND Instruction. An illegal instruction, $4AFA, is reserved for use by develop-
ment tools. The CPU32+ defines $4AFA (BGND) to be a BDM entry point when BDM is
enabled. If BDM is disabled, an illegal instruction trap is acknowledged. Illegal instruction
traps are discussed in 5.5.2.8 Illegal or Unimplemented Instructions.
5.6.2.2.3 Double Bus Fault. The CPU32+ normally treats a double bus fault (two bus faults
in succession) as a catastrophic system error and halts. When this condition occurs during
initial system debug (a fault in the reset logic), further debugging is impossible until the prob-
lem is corrected. In BDM, the fault can be temporarily bypassed so that its origin can be iso-
lated and eliminated.
5.6.2.3 ENTERING BDM. When the processor detects a BKPT or a double bus fault or
decodes a BGND instruction, it suspends instruction execution and asserts the FREEZE
output. FREEZE assertion is the first indication that the processor has entered BDM. Once
FREEZE has been asserted, the CPU enables the serial communication hardware and
awaits a command.
The CPU writes a unique value indicating the source of BDM transition into temporary reg-
ister A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP and deter-
mine the source (see Table 5-20) by issuing a read system register command (RSREG).
ATEMP is used in most debugger commands for temporary storage—it is imperative that
the RSREG command be the first command issued after transition into BDM.
A double bus fault during initial SP/PC fetch sequence is distinguished by a value of
$FFFFFFFF in the current instruction PC. At no other time will the processor write an odd
value into this register.
5.6.2.4 COMMAND EXECUTION. Figure 5-21 summarizes BDM command execution.
Commands consist of one 16-bit operation word and can include one or more 16-bit exten-
sion words. Each incoming word is read as it is assembled by the serial interface. The micro-
code routine corresponding to a command is executed as soon as the command is
complete. Result operands are loaded into the output shift register to be shifted out as the
next command is read. This process is repeated for each command until the CPU returns to
normal operating mode.
5-62
*SSW is described in detail in 5.5.3 Fault Recovery.
Hardware Breakpoint
BGND Instruction
Double Bus Fault
Source
Table 5-20. Polling the BDM Entry Source
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ATEMP 31–16
$0000
$0000
SSW*
ATEMP 15–0
$FFFF
$0001
$0000
MOTOROLA