IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 108

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
Table 42: Various Operation Modes in Transmit Path for Reference (Continued)
4.1.3
reference.
4.1.3.1
must be set to ‘0’ to enable the HDLC data link position for receive path.
one of the three HDLC Receive data links must be selected in the
RHDLCSEL[1:0] (b7~6, E1-00AH). Then the HDLC data link can be con-
figured to extract from even and/or odd frames, from any time slot, and
from any bit. The following examples show how to select the HDLC
Receiver data link positions:
Receive #1:
Receive #1:
HDLC Receive #2:
Operation
Note:
1. In the ‘Register’ column, except for the Transmit Multiplexed mode, the register position of the Framer 1 is listed to represent the set of the registers of eight framers. The other registers
positions are tabulated in the ‘Register Map’. However, in the Transmit Multiplexed mode, the registers positions of eight framers are all listed.
2. The ‘Description’ illustrates the fundamental function of the operation mode. The others can be configured as desired.
Transmit Multi-
plexed Mode
(Continued)
In this chapter, some common operation examples are given for
Before using the HDLC Receiver, the TXCISEL (b3, E1-00AH)
Since three HDLC Receive data links are integrated in one framer,
a. Extract the HDLC data link from all bits of TS16 in HDLC
- set the TXCISEL (b3, E1-00AH) to ‘0’;
- set the RHDLCSEL[1:0] (b7~6, E1-00AH) to ‘00’;
- set the DL1_EVEN (b7, E1-028H) to ‘0’;
- set the DL1_ODD (b6, E1-028H) to ‘0’;
- set the TS16_EN (b5, E1-028H) to ‘1’.
b. Extract the HDLC data link from the Sa8 National bit in HDLC
- set the TXCISEL (b3, E1-00AH) to ‘0’;
- set the RHDLCSEL[1:0] (b7~6, E1-00AH) to ‘00’;
- set the DL1_EVEN (b7, E1-028H) to ‘0’;
- set the DL1_ODD (b6, E1-028H) to ‘1’;
- set the TS16_EN (b5, E1-028H) to ‘0’;
- set the DL1_TS[4:0] (b4~0, E1-028H) to ‘00000’;
- set the DL1_BIT[7:0] (b7~0, E1-029H) to ‘00000001’.
c. Extract the HDLC data link from all bits of TS20 of all frames in
- set the TXCISEL (b3, E1-00AH) to ‘0’;
- set the RHDLCSEL[1:0] (b7~6, E1-00AH) to ‘01’;
- set the DL2_EVEN (b7, E1-02AH) to ‘1’;
- set the DL2_ODD (b6, E1-02AH) to ‘1’;
- set the DL2_TS [4:0] (b4~0, E1-02AH) to ‘10100’;
- set the DL2_BIT [7:0] (b7~0, E1-02BH) to ‘11111111’.
Mode
OPERATION EXAMPLE
Using HDLC Receiver
Register
0A7H
1A7H
2A7H
3A7H
027H
127H
227H
327H
1
Value (from Bit7 to Bit0)
00010000
00010000
00010000
00010000
00010000
00010000
00010000
00010000
The FIFO is set to self-center its read pointer.
98
HDLC Receiver should be enabled by setting the EN (b0, E1-048H) to
logic 1. If needed, set the MEN (b3, E1-048H) and the MM (b2, E1-
048H) to determine which Address Matching Mode to be used (refer to
Chapter 5.2 Register Description for details). After setting these 3 bits,
the RHDLC Primary Address Match register and the RHDLC Secondary
Address Match register should be set to proper values. If the INTC[6:0]
(b6~0, E1-049H) are set, whenever the number of bytes in the RHDLC
FIFO exceeds the value set in the INTC[6:0] (b6~0, E1-049H), the INTR
(b0, E1-04AH) will be set to logic 1. This interrupt will persist until the
RHDLC FIFO becomes empty. Setting the INTE (b7, E1-049H) to logic 1
allows the internal interrupt status to be propagated to the INT output
pin.
received in a polled or interrupt driven mode.
- Interrupt Driven Mode
asserted, the source of the interrupt should be first identified by reading
the Interrupt ID register and Interrupt Source registers. If the source of
the interrupt is HDLC Receive, the Interrupt Service procedure will be
carried out as shown in Figure 73.
- Polling Mode
except that the entry of the service is from a local timer rather than an
interrupt.
After setting the HDLC data link position properly, the selected
After setting these registers properly, the HDLC data can be
When the INTE (b7, E1-049H) is set to logic 1, if the INT pin is
In polling mode, the operation procedure is the same as Figure 73,
Description
2
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009