IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 236

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
T1 / J1 FRMP Interrupt Enable (021H, 0A1H, 121H, 1A1H, 221H, 2A1H, 321H, 3A1H)
COFAE:
decides whether to generate an interrupt or not.
FERE:
BEEE:
ted data and a CRC-6 error (the local calculated CRC-6 result is not the same as the received CRC-6 bits) for ESF formatted data.
SFEE:
MFPE:
decides whether to generate an interrupt when Mimic Framing Pattern appears or disappears.
tern.
INFRE:
frame to in-frame.
Programming Information
Bit Name
Default
Bit No.
Type
When the frame alignment pattern has been achieved and the position of the new frame alignment pattern differs from the previous one, this bit
= 0: Disable the interrupt when there is a shift on the framing signal position.
= 1: Enable the interrupt on the INT pin when there is a shift on the framing signal position.
= 0: No interrupt is generated when there is a framing bit error.
= 1: An interrupt on the INT pin is generated when a framing bit error is detected.
= 0: No interrupt is generated when there is a bit error event.
= 1: An interrupt on the INT pin is generated when a bit error event occurs. Here, the bit error event is defined as a framing bit error for SF format-
(In SF mode, this bit has the same function as the FERE.)
The Severe Framing Error is defined as 2 or more framing bit errors during the current super-frame of SF or ESF data.
= 0: No interrupt is generated when there is a Severe Framing Error.
= 1: An interrupt on the INT pin is generated when Severe Framing Error event occurs.
Mimic Framing Pattern is defined as more than one framing alignment pattern existing simultaneously in the receiving data stream. This bit
= 0: No interrupt is generated when there is a transition of the status of Mimic Framing Pattern.
= 1: An interrupt on the INT pin is generated when there is a transition (exist to non-exist, or non-exist to exist) of the status of Mimic Framing Pat-
This bit decides whether to generate an interrupt when the status of incoming data stream changes from in-frame to out-of-frame or from out-of-
= 0: No interrupt is generated when there is a transition of Frame Synchronization Status.
= 1: An interrupt on the INT pin is generated when there is a transition of Framing Synchronization Status.
7
Reserved
6
COFAE
R/W
5
0
FERE
R/W
4
0
226
BEEE
R/W
3
0
SFEE
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
MFPE
R/W
1
0
March 5, 2009
INFRE
R/W
0
0