IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 201

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
SIGNINV, RINV[1:0]:
the pattern generated in the PRGD; Invert the bit.
E1 RPLC Data Trunk Conditioning Code Byte Registers (RPLC Indirect Registers 40H ~ 5FH)
registers-20~3FH) is logic 1. The DTRK7 is the MSB.
E1 RPLC Signaling Trunk Conditioning Byte Registers (RPLC Indirect Registers 61H ~ 7FH)
registers-20~3FH) is logic 1. They are in the least significant nibble.
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
The SIGNINV and the RINV[1:0] bits select the bits in the corresponding time slot to be inverted when output on the RSDn/MRSD pin:
The priority of the RPLC operation on the RSDn pin from high to low is:
Extract data to PRGD for test; Replace the data with the value in the DTRK[7:0]; Replace the data with the milliwatt pattern; Replace the data with
They contain the data that will replace the data output on the RSDn/MRSD pin when the corresponding bit DTRKC/NxTS (b6, E1-RPLC-indirect
These bits contain the data that will replace the data output on the RSSIGn/MRSSIG pin when the corresponding STRKC (b5, E1-RPLC-indirect
DTRK7
R/W
SIGNINV
X
7
7
0
0
0
0
1
1
1
1
DTRK6
RINV[1:0]
R/W
6
X
6
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Reserved
DTRK5
R/W
X
5
5
Invert the even bits (2, 4, 6, 8) of the time slot (bit 1 is the MSB)
Invert the odd bits (1, 3, 5, 7) of the time slot (bit 1 is the MSB)
Invert all the bits of the time slot except the MSB (bit1)
DTRK4
Invert the bits 1, 2, 4, 6 and 8 of the time slot
R/W
X
4
4
Invert the bits 3, 5 and 7 of the time slot
191
Invert the bit 1 (MSB) of the time slot
Invert all the bits of the time slot
Bits Inverted
No inversion
DTRK3
R/W
R/W
X
A
X
3
3
DTRK2
R/W
R/W
2
X
2
B
X
T1 / E1 / J1 OCTAL FRAMER
DTRK1
R/W
R/W
X
C
X
1
1
March 5, 2009
DTRK0
R/W
R/W
X
D
X
0
0