IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 193

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
E1 THDLC #1, #2, #3 Configuration (050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H)
E1-00AH).
FLGSHARE:
FIFOCLR:
EOM:
data byte transmitted.
ABT:
in the FIFO will be lost.
transitions from logic 0 to logic 1.
CRC:
EN:
EOM is set to logic 1.
Programming Information
Bit Name
Default
Bit No.
Type
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4,
= 0: The opening flag of the next HDLC frame and closing flag of the current HDLC frame are separate.
= 1: The opening flag of the next HDLC frame and closing flag of the current HDLC frame are shared
= 0: Normal operation.
= 1: Clear the FIFO.
= 0: Normal operation.
= 1: A positive transition of this bit starts a packet transmission. Then if the CRC(b1, E1-050H) is set, the 16-bit FCS word is appended to the last
= 0: Normal operation.
= 1: Transmit the 7F abort sequence after the current setting in the Transmit Data register is transmitted, so that the FIFO is cleared and all data
Aborts are continuously sent and the FIFO is held in reset until this bit is reset to a logic 0. At least one Abort sequence will be sent when the ABT
= 0: Do not append the CRC-16 frame check sequences (FCS) to the end of the HDLC data.
= 1: Append the FCS to the end of the HDLC data.
= 0: Disable the operation of the THDLC block.
= 1: Enable the operation of the THDLC block and flag sequences are sent until data is written into the THDLC Transmit Data register and the
FLGSHARE
R/W
7
1
FIFOCLR
R/W
6
0
5
Reserved
4
183
EOM
R/W
3
0
ABT
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
CRC
R/W
1
1
March 5, 2009
R/W
EN
0
0