IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 126

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
example is shown in Table 54.
4.2.4.2
format. Before using the HDLC#2 Transmit, the TXCISEL (b3, T1/J1-
00DH) must be set to ‘1’ to enable the HDLC data link position for trans-
mit path.
one of the two HDLC Transmit data links must be chosen in the
THDLCSEL[1:0] (b5~4, T1/J1-00DH). The THDLC #1 can only insert to
F-bit of each odd frame. The THDLC #2 can be set to insert to even and/
or odd frames, to any channel, and to any bit. The follow is an example
for selecting the HDLC Transmit data link positions in THDLC #2:
HDLC Transmit #2:
HDLC Transmit should be enabled by setting the EN (b0, T1/J1-034H) to
logic 1. The FIFOCLR (b6, T1/J1-034H) should be set and then cleared
to initialize the THDLC FIFO.
Sequences (FCS) generation is desired. Set the FULLE (b3, T1/J1-
037H), OVRE (b2, T1/J1-037H), UDRE (b1, T1/J1-037H) and LFILLE
(b0, T1/J1-037H) to logic 1 if interrupt driven mode is used. Set THDLC
Upper Transmit Threshold and THDLC Lower Transmit Threshold regis-
ters to the desired values. If a complete packet has been written into
THDLC FIFO, the EOM (b3, T1/J1-034H) should be set.
mitted in a polled or interrupt driven mode.
Operation
Table 54: Example for Using HDLC Receiver
Then read the data status in register 056H. Until a complete packet is
received, read the data from register 057H.
Register
00DH
070H
071H
054H
055H
058H
059H
To summarize the procedure of using HDLC Receive, a complete
In T1/J1 mode, the HDLC Transmit can only be used in the ESF
Since two HDLC Transmit data links are integrated in one framer,
a. Insert the HDLC data link to all bits of channel 20 of all framers in
- set the TXCISEL (b3, T1/J1-00DH) to ‘1’;
- set the THDLCSEL[1:0] (b5~4, T1/J1-00DH) to ‘01’;
- set the DL2_EVEN (b7, T1/J1-070H) to ‘1’;
- set the DL2_ODD (b6, T1/J1-070H) to ‘1’;
- set the DL2_TS[4:0] (b4~0, T1/J1-070H) to ‘10100’;
- set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to ‘11111111’.
After setting the HDLC data link position properly, the selected
Set the CRC (b1, T1/J1-034H) to logic 1 if the Frame Check
After setting these registers properly, the HDLC data can be trans-
Value
FFH
0DH
FFH
50H
8FH
13H
Using HDLC Transmitter
C4H
RHDLC #2 is selected. The HDLC Receive is accessi-
ble to the CPU interface.
TS4 of even frames and odd frames is selected.
All 8 bits are selected.
The function of the RHDLC #2 is enabled. Set
address match mode.
Set the INTE to ‘1’. When the number of bytes in the
RHDLC FIFO exceeds 15, an interrupt is generated.
The primary address is set to 13H.
The secondary address is set to FFH.
Description
the
116
- Interrupt Driven Mode
HDLC data if the end of a packet was written or if the THDLC FIFO fill
level reaches the Upper Transmit Threshold. The writing procedure is
shown in Figure 80.
UDRE (b1, T1/J1-037H) and LFILLE (b0, T1/J1-037H) are set to logic 1,
the source of the interrupt should be identified firstly by reading the Inter-
rupt ID register and Interrupt Source registers if the INT pin is asserted.
If the source of the interrupt is HDLC Transmit, the Interrupt Service pro-
cedure will be carried out as shown in Figure 81.
Figure 80. Writing Data to T1/J1 Mode THDLC FIFO
Writing HDLC data to THDLC FIFO, the THDLC will transmit the
When the FULLE (b3, T1/J1-037H), OVRE (b2, T1/J1-037H),
Data is available
Write data into
End of packet
THDLC FIFO
THDLC Initial
Set EOM
Y
Y
T1 / E1 / J1 OCTAL FRAMER
N
N
March 5, 2009