IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 143

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
E1 Receive Side System Interface Options (001H, 081H, 101H, 181H, 201H, 281H, 301H, 381H)
LRCKFALL:
RSSIG_EN:
attenuated version of LRCKn or an 8 KHz clock.
data. Each time-slot signaling bits are time slot aligned with RSDn data stream and located in the lower nibble (b5b6b7b8).
RSCKSEL:
MRBS:
MRBC:
complete the setting in the MRBS (b4, E1-001H) before enabling this bit. This bit of the framers that are output to the same multiplexed bus must be
set to the same value.
OOSMFAIS:
multi-frame. This bit affects the corresponding time slot of the MRSSIGn data stream if the multiplexed bus is enabled.
TRKEN:
tution. The ELSB Idle Code can still be overwritten by the contents in RPLC Data Trunk Conditioning Registers and Signaling Trunk Conditioning Reg-
Programming Information
AUTOUPDATE:
Bit Name
Default
Bit No.
Type
This bit decides whether the PMON and PRGD registers are automatically updated once every second.
= 0: The PMON and PRGD registers are not automatically updated. They can only be updated by MCU operation.
= 1: The PMON and PRGD registers will be automatically updated once every second.
This bit chooses the active edge of LRCKn to sample the data on the corresponding LRDn.
= 0: the rising edge is chosen.
= 1: the falling edge is chosen.
When the Receive Clock Slave Mode is enabled (RSCKSLV = 1, b5, E1-010H), this bit configures the receive side system interface.
= 0: the Receive Clock Slave RSCK Reference Mode is enabled. The RSCKn/RSSIGn pin will be used as RSCKn to output a 2.048 MHz jitter
= 1: the Receive Clock Slave External Signaling mode is enabled. The RSCKn/RSSIGn pin is used as RSSIGn to output the extracted signaling
When the Receive Clock Slave RSCK Reference Mode is enabled, this bit chooses the frequency of RSCKn.
= 0: RSCKn outputs an 8 KHz timing reference that is generated by dividing the jitter attenuated version of LRCKn.
= 1: RSCKn outputs a jitter attenuated version of the 2.048 MHz Line Receive Clock (LRCKn).
In the Receive Multiplexed mode, this bit decides which bus the corresponding framer will use to output the received data.
= 0: The first multiplexed bus (MRSD[1], MRSFS[1], MRSSIG[1]) is chosen.
= 1: The second multiplexed bus (MRSD[2], MRSFS[2], MRSSIG[2]) is chosen.
This bit turns on or off the transmission of received data from the corresponding framer to the selected multiplexed receive bus. Users should
= 0: The corresponding framer will not output its data stream on the multiplexed bus.
= 1: The corresponding framer will output its data stream on the multiplexed bus.
This bit decides whether to send Alarm Indication Signals (All Ones Signals) on RSSIGn to the system side in the condition of out of signaling
= 0: The output on the RSSIGn/MRSSIG pin will not be affected by the indication of out of Signaling Multi-Frame.
= 1: The output on the RSSIGn/MRSSIG pin will be set to all ‘One’s in the condition of out of Signaling Multi-Frame.
This bit decides whether to substitute the data on RSDn with the contents in the ELSB Idle Code Register during out of Basic frame. After substi-
LRCKFALL
R/W
7
0
RSSIG_EN
R/W
6
1
RSCKSEL
R/W
5
0
MRBS
R/W
4
0
133
MRBC
R/W
3
0
OOSMFAIS
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
TRKEN
R/W
1
0
March 5, 2009
RXMTKC
R/W
0
0