IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 63

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
3.11.2.4
tional T1/J1 mode, if the RPRTYE (b0, T1/J1-002H) is logic 1, parity
check will be conducted over the bits in the previous frame and the
result is inserted into the F-bit on the RSDn/MRSD and RSSIGn/MRS-
SIG pins. The even parity or odd parity is chosen by the RPTYP (b1, T1/
J1-002H) and whether the F-bit is calculated or not is determined by the
PTY_EXTD (b3, T1/J1-002H).
3.11.2.5
T1/J1 mode E1 rate mode) or 8.192MHz (in Receive Multiplexed mode),
channel offset and/or bit offset between RSCFS and the start of the cor-
Functional Description
Table 25: Receive System Interface Bit Offset
MRSSIG
MRSCFS
MRSCCK
MRSFS
(b1, T1/J1-003)
MRSD
MRSSIG
RSCFSFALL
MRSD
MRSFS
In all the above modes except for the Receive Clock Slave Frac-
When the system clock rate is 2.048MHz (in Receive Clock Slave
1
1
0
0
C
7
When the RSD_RSCFS_EDGE (b5, T1/J1-078H) is logic 0:
When the RSD_RSCFS_EDGE (b5, T1/J1-078H) is logic 1:
C
7
8
D
Parity
D
8
bit
Parity Check
Offset
P
P
Parity
bit
P
P
X
X
(b0, T1/J1-003H)
X
X
RSCCKRISE
X
X
X
X
Framer1
X
X
Framer1
0
1
0
1
X
X
Figure 34. T1/J1 Receive Multiplexed Mode - Functional Timing Example 2
X
X
X
X
The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3
X
X
are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the BOFF_EN of the four Framers are set to logic 0:
X
X
X
X
X
X
F-bit
F
X
F-bit
F
X
Parity
bit
000
P
P
Parity
2
1
1
2
The RSCCKRISE(b0, T1/J1-003H) is logic 1 and the RSCFSFALL (b1, T1/J1-003H) is logic 1.
P
bit
P
In this example, Framer1 to Frame4 are supposed to be multiplexed to one multiplexed bus.
X
X
The CMS (b4, T1/J1-078H) is logic 1, i.e., the bankplane clock rate is 16.384Mbit/s.
X
X
X
X
X
X
Framer2
X
X
Framer2
X
X
001
X
X
4
3
3
4
X
X
X
X
X
X
X
X
F-bit
X
X
F
X
F-bit
X
F
Parity
010
bit
P
P
6
5
5
6
Parity
P
bit
P
X
X
X
X
53
X
X
X
X
Framer3
responding frame on RSDn/MRSD (and RSSIGn/MRSSIG) can be con-
figured. Bit offset is disabled when the CMS (b4, T1/J1-078H) is logic 1.
077H). The TSOFF[6:0] (b6~0, E1-013H) give a binary representation.
ured in the BOFF[2:0] (b2~0, T1/J1-078H). The bit offset follows the
Concentration Highway Interface (CHI) specification (refer to Table 25).
The CET (clock edge transmit) is counted from the active edge of
RSCFS/MRSCFS (refer to the example in Figure 34). The pulse on
RSFSn/MRSFS and the signal on RSSIGn/MRSSIG (if it exists) are
aligned to RSDn/MRSD.
X
X
BOFF[2:0] (b2~0, T1/J1-078H)
Framer3
X
X
011
X
X
8
7
7
8
The channel offset is configured in the TSOFF[6:0] (b6~0, T1/J1-
Enabled by the BOFF_EN (b3, T1/J1-078H), the bit offset is config-
X
X
X
X
X
X
X
X
X
X
F-bit
F
X
F-bit
F
X
Parity
100
10
10
bit
9
9
P
P
Parity
P
bit
P
X
X
X
X
X
X
X
X
Framer4
X
X
Framer4
101
X
X
12
12
11
11
X
X
X
X
X
X
X
X
X
X
(The 'X' represents the filled bits and has no meaning.)
X
X
T1 / E1 / J1 OCTAL FRAMER
F-bit
F
X
110
F-bit
14
13
13
14
F
X
X
1
1
X
X
2
X
2
3
X
3
X
Framer1_CH1
111
16
15
15
16
X
4
Framer1_CH1
4
X
March 5, 2009
A
5
A
5
6
B
6
B
7
C
CET
C
7
D
8
D
8