IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 7

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

List of Tables
Table 1: Structure of TS0 of CRC Multi-Frame .......................................................................................................................................................... 15
Table 2: Interrupt Sources in the E1 Frame Processor .............................................................................................................................................. 16
Table 3: SF Format .................................................................................................................................................................................................... 18
Table 4: ESF Format .................................................................................................................................................................................................. 18
Table 5: Interrupt Sources in the T1/J1 Frame Processor ......................................................................................................................................... 19
Table 6: Basic Frame Alignment Pattern Error Counter ............................................................................................................................................ 20
Table 7: Alarm Summary in ALMD ............................................................................................................................................................................ 21
Table 8: A-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 28
Table 9: µ-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 28
Table 10: E1 Mode Receive System Interface in Different Operation Modes ............................................................................................................. 30
Table 11: Operation Mode Selection in E1 Receive Path ............................................................................................................................................ 30
Table 12: Active Edge Selection of RSCCK (in E1 Receive Clock Slave RSCK Reference Mode) ............................................................................ 31
Table 13: Active Edge Selection of RSCCK (in E1 Receive Clock Slave External Signaling Mode) ........................................................................... 33
Table 14: Active Edge Selection of RSCK (in E1 Receive Clock Master Mode) ......................................................................................................... 35
Table 15: Active Edge Selection of MRSCCK (in E1 Receive Multiplexed Mode) ...................................................................................................... 39
Table 16: Offset in Different Operation Modes ............................................................................................................................................................ 41
Table 17: Receive System Interface Bit Offset (FPMODE [b5, E1-011H] = 0) ............................................................................................................ 41
Table 18: Receive System Interface Bit Offset (FPMODE [b5, E1-011H] = 1) ............................................................................................................ 41
Table 19: Bit Offset Between RSFSn and RSDn When the BRXSMFP and the ALTIFP (b2, b0, E1-011H) are Both Set To Logical 1 ..................... 43
Table 20: T1/J1 Mode Receive System Interface in Different Operation Modes ......................................................................................................... 44
Table 21: Operation Mode Selection in T1/J1 Receive Path ....................................................................................................................................... 44
Table 22: Active Edge Selection of RSCCK (in T1/J1 Receive Clock Slave RSCK Reference Mode) ....................................................................... 45
Table 23: Active Edge Selection of RSCCK (in T1/J1 Receive Clock Slave External Signaling Mode) ...................................................................... 47
Table 24: Active Edge Selection of MRSCCK (in T1/J1 Receive Multiplexed Mode) .................................................................................................. 52
Table 25: Receive System Interface Bit Offset ............................................................................................................................................................ 53
Table 26: E1 Mode Transmit System Interface in Different Operation Modes ............................................................................................................ 57
Table 27: Operation Mode Selection in E1 Transmit Path ........................................................................................................................................... 57
Table 28: Active Edge Selection of TSCCKB (in E1 Transmit Clock Slave TSFS Enable Mode) ............................................................................... 58
Table 29: Active Edge Selection of TSCCKB (in E1 Transmit Clock Slave External Signaling Mode) ........................................................................ 60
Table 30: Active Edge Selection of MTSCCKB (in E1 Transmit Multiplexed Mode) ................................................................................................... 63
Table 31: Transmit System Interface Bit Offset (CHI [b3, E1-01CH] = 1, CMS [b2, E1-018H] = 0) ............................................................................ 66
Table 32: Transmit System Interface Bit Offset (CHI [b3, E1-01CH] = 1, CMS [b2, E1-018H] = 1) ............................................................................ 66
Table 33: T1/J1 Mode Transmit System Interface in Different Operation Modes ........................................................................................................ 69
Table 34: Operation Mode Selection in T1/J1 Transmit Path ...................................................................................................................................... 69
Table 35: Active Edge Selection of TSCCKB (in T1/J1 Transmit Clock Slave TSFS Enable Mode) ........................................................................... 70
Table 36: Remote Alarm Indication ............................................................................................................................................................................. 80
Table 37: Content in International Bits (when the INDIS [b1, E1-040H] is logic 0) ...................................................................................................... 80
Table 38: Interrupt Summary in E1 Mode .................................................................................................................................................................... 81
Table 39: Default Setting in Receive Path in E1 Mode ................................................................................................................................................ 94
Table 40: Default Setting in Transmit Path in E1 Mode ............................................................................................................................................... 94
Table 41: Various Operation Modes in Receive Path for Reference ........................................................................................................................... 95
Table 42: Various Operation Modes in Transmit Path for Reference .......................................................................................................................... 96
Table 43: Example for Using HDLC Receiver ........................................................................................................................................................... 100
Table 44: Example for Using HDLC Transmitter ....................................................................................................................................................... 102
Table 45: Test Pattern in E1 Mode ............................................................................................................................................................................ 103
Table 46: Setting of PRGD ........................................................................................................................................................................................ 104
Table 47: Initialization of TPLC .................................................................................................................................................................................. 104
Table 48: Initialization of RPLC ................................................................................................................................................................................. 105
March 5, 2009
List of Tables
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