IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 280

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
6.2
6.2.1
ufacturer Identity and a fixed bit. The IDR is 32 bits long and is parti-
tioned as in Table 67. Data from the IDR is shifted out to the TDO LSB
first.
6.2.2
between the TDI input and TDO output, bypassing the BYR to reduce
test access times.
6.2.3
sample and control the state of an external signal during BS tests. When
used as output, the cells are able to control the state of an external sig-
nal during BS tests.
are able to sample and control the state of an external signal. When con-
figured as output, the cells are able to control the state of an external
signal.
directional or tri-state output pins during BS tests.
trated in Table 68:
IEEE STD 1149.1 JTAG Test Access Port
Table 67: IDR
Table 68: Boundary Scan Sequence & I/O Pad Cell Type
The IDR can be set to define the Vision, the Part Number, the Man-
The BYR consists of a single bit. It can provide a serial path
The scan chain uses 3 types of cells:
- Input / Output cells: When used as input, the cells are able to
- In/Out or Tri-state output cells: When configured as input, the cells
- Control cell: This cell provides a signal for direction control of bi-
The Boundary Scan sequence and the I/O Pad Cell type are illus-
BIT No.
12 ~ 27
28 ~ 31
1 ~ 11
JTAG DATA REGISTER
DEVICE IDENTIFICATION REGISTER (IDR)
BYPASS REGISTER (BYR)
BOUNDARY SCAN REGISTER (BSR)
0
Pin_name
LRCK[1]
LRCK[2]
LRCK[3]
LRCK[4]
LTCK[1]
LRD[1]
LRD[2]
LRD[3]
LRD[4]
LTD[1]
LTD[2]
Manufacturer Identity (033H)
Cell Type
Part Number (04D0H)
Output
Output
Output
COMMENTS
Input
Input
Input
Input
Input
Input
Input
Input
Version (2H)
Set to ‘1’
BS *
128
127
126
125
124
123
122
121
120
119
118
270
Table 68: Boundary Scan Sequence & I/O Pad Cell Type
Pin_name
D[7:0]_EN
LRCK[5]
LRCK[6]
LRCK[7]
LRCK[8]
LTCK[2]
LTCK[3]
LTCK[4]
LTCK[5]
LTCK[6]
LTCK[7]
LTCK[8]
LRD[5]
LRD[6]
LRD[7]
LRD[8]
LTD[3]
LTD[4]
LTD[5]
LTD[6]
LTD[7]
LTD[8]
RST
ALE
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
INT
T1 / E1 / J1 OCTAL FRAMER
Cell Type
Control
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
March 5, 2009
BS *
109
108
107
106
105
104
103
102
101
100
117
116
115
114
113
112
111
110
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75