IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 165

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
E1 RHDLC Receive Data Link 2 Control (TXCISEL = 0) (02AH, 0AAH, 12AH, 1AAH, 22AH, 2AAH, 32AH, 3AAH)
DL2_EVEN:
DL2_ODD:
DL2_TS[4:0]:
‘0’.
E1 RHDLC Data Link 2 Bit Select (TXCISEL = 0) (02BH, 0ABH, 12BH, 1ABH, 22BH, 2ABH, 32BH, 3ABH)
DL2_BITn:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
When the TXCISEL (b3, E1-00AH) is ‘0’, this register is used for the Receive HDLC #2.
= 0: The data is not extracted from the even frames.
= 1: The data is extracted from the even frames.
The even frames are FAS frames.
= 0: The data is not extracted from the odd frames.
= 1: The data is extracted from the odd frames.
The odd frames are NFAS frames.
These bits represent the binary value of the time slot to extract the data from. They are invalid when the DL2_EVEN and the DL2_ODD are both
When the TXCISEL (b3, E1-00AH) is ‘0’, this register is used for the Receive HDLC #2.
= 0: The data is not extracted from the corresponding bit.
= 1: The data is extracted from the corresponding bit of the assigned time slot.
These bits are invalid when the DL2_EVEN and the DL2_ODD are both ‘0’.
The DL2_BIT[7] corresponds to the first bit (MSB) of the selected time slot.
DL2_EVEN
DL2_BIT[7]
R/W
R/W
7
0
7
0
DL2_BIT[6]
DL2_ODD
R/W
R/W
6
0
6
0
DL2_BIT[5]
Reserved
R/W
5
5
0
DL2_BIT[4]
DL2_TS[4]
R/W
R/W
4
0
4
0
155
DL2_BIT[3]
DL2_TS[3]
R/W
R/W
3
0
3
0
DL2_BIT[2]
DL2_TS[2]
R/W
R/W
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
DL2_BIT[1]
DL2_TS[1]
R/W
R/W
1
0
1
0
March 5, 2009
DL2_BIT[0]
DL2_TS[0]
R/W
R/W
0
0
0
0