IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 153

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
slots. The time slots selection is decided by the DTRKC/NxTS (b6, E1-RPLC-Indirect Register-20-3F H).
this configuration, bits from the second bit of TS 26 to the last bit of the Basic Frame are suppressed, and the remaining bits can be gapped by setting
the DTRKC/NxTS (b6, E1-RPLC-Indirect Register-20-3F H).
RSCKSLV:
DE:
FE:
CMS:
RATE[1:0]:
in all eight framers should be configured to select the 8.192 Mbit/s backplane bit rate. When the RATE[1:0] select the 8.192 Mbit/s, the RSCKSLV (b5,
E1-010H) must be set to ‘1’.
Programming Information
‘Full E1’ mode means that the received entire frame (256 bits) is clocked out from the RSDn pin, and there are no gaps in the RSCKn clock pulse.
‘Fractional E1’ mode means that RSCKn only clocks out on the selected time slots, and RSCKn does not pulse during those un-selected time
‘Fractional E1 with F-bit’ mode is to support ITU recommendation G.802 where 1.544 Mbit/s data is carried within a 2.048 Mbit/s data stream. In
= 0: Receive Clock Master mode is enabled.
= 1: Received Clock Slave mode is enabled.
This bit must be set to ‘1’ to support multiplexed backplane.
= 0: The signal on the RSDn and RSSIGn pins is updated on the falling edge of RSCCK or the RSCK.
= 1: The signal on the RSDn and RSSIG pins is updated on the rising edge of RSCCK or the RSCK.
In Receive Multiplexed mode, the DE in all eight framers should be set to the same value.
If the FE is not equal to the DE, the frame pulse will be sampled or updated one clock edge after the corresponding data pulse.
= 0: The signal on the RSCFS pin is sampled or signal on the RSFSn pin is updated on the falling edge of RSCCK or RSCKn.
= 1: The signal on the RSCFS pin is sampled or signal on the RSFSn pin is updated on the rising edge of RSCCK or the RSCKn.
In Receive Multiplexed mode, the FE in all eight framers should be set to the same value.
= 0: The clock frequency of RSCCK/MRSCCK is the same as the bit rate of the backplane.
= 1: The clock frequency of RSCCK/MRSCCK is double the bit rate of the backplane.
The CMS of all eight framers should be set to the same value.
These bits determine the bit rate of the received data stream on the backplane. Note that to operate in Receive Multiplexed mode, the RATE[1:0]
RATE[1:0]
0 0
0 1
1 0
1 1
143
Backplane Rate
2.048M bit/s
8.192M bit/s
Reserved
Reserved
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009