IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 45

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
3.11.1.2
signal on the RSCKn pin and framing signal on the RSFSn pin to output
the data on each RSDn pin. As the common framing signal RSCFS is
not used, the FPMODE bit (b5, E1-011H) must be set to ‘0’.
2.048Mb/s.
the PERTS_RSFS (b3, E1-00EH) and REF_MRSFS (b2, E1-00EH) to
output all zeros, to indicate the frame position or to output the same
pulse as RSCFS. When it is defined to indicate the frame position, it can
indicate the first bit of a Basic Frame, Signaling Multi-Frame, CRC-Multi-
frame, or both the Signaling and CRC-multiframe. This selection is made
by the ROHM, BRXSMFP, BRXCMFP, ALTIFP (b3, b2, b1, b0, E1-
011H). When RSFSn is used for framing pulse indication, the valid polar-
ity of it is configured by the FPINV (b6, E1-011H). In this case, if the
FPMODE (b5, E1-011H) is low, RSFSn can only indicate the Basic
Frame no matter what the setting in the ROHM, BRXSMFP, BRXCMFP,
ALTIFP (b3, b2, b1, b0, E1-011H) is.
face is clocked by RSCKn. The active edge of RSCKn used to update
the data on RSDn and RSFSn is determined by the DE (b4, E1-010H)
and the FE (b3, E1-010H) respectively as shown in Table 14.
Functional Description
In the Receive Clock Master mode, each framer uses its own clock
In the Receive Clock Master Mode, the bit rate on the RSDn pin is
In the Receive Clock Master Mode, RSFSn can be configured by
In the Receive Clock Master Mode, the data on the system inter-
Receive Clock Master Mode
RSD[1:8] *
RSFS[1:8] *
RSCK[1:8]
Note: * RSD, RSFS are timed to RSCK
Figure 15. Receive Clock Master Full E1 or T1/J1 Mode
Interface
Receive
System
Processor
Frame
35
Clock Master Full E1 Mode and Receive Clock Master Fractional E1
(with F-bit) Mode.
Table 14: Active Edge Selection of RSCK (in E1 Receive Clock
Master Mode)
3.11.1.2.1
Master mode, the special feature in this mode (refer to Figure 15) is that
RSCKn is a standard 2.048MHz clock, and the data in all 32 time slots in
a standard E1 frame is clocked out by RSCKn.
slot is the first bit to be output.
Note:
If the setting in the FE (b3, E1-010H) and DE (b4, E1-010H) is different, RSFSn will be
one clock edge ahead of RSDn.
The Receive Clock Master Mode includes two sub-modes: Receive
Besides all the common functions described in the Receive Clock
Figure 16 shows the functional timing examples. Bit 1 of each time
RSFSn
RSDn
RECEIVER
Receive Clock Master Full E1 Mode
DPLL
FIFO
the Bit Determining the Active Edge of RSCKn
T1 / E1 / J1 OCTAL FRAMER
DE (b4, E1-010H)
FE (b3, E1-010H)
LRCK[1:8]
LRD[1:8]
March 5, 2009