IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 277

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
T1 / J1 RESI Time Slot Offset (078H, 0F8H, 178H, 1F8H, 278H, 2F8H, 378H, 3F8H)
FPINV:
RSD_RSCFS_EDGE:
003H) are equal.
is used to update the signal on the MRSD, MRSSIG and MRSFS pins.
is used to update the signal on the MRSD, MRSSIG and MRSFS pins.
CMS:
BOFF_EN:
BOFF[2:0]:
001H] are set to ‘10’), these bits determine the bit offset between RSCFS and the start of the corresponding frame on RSDn (and RSSIGn).
SIG.
Interface (CHI) specification. Refer to the Function Description for details.
Programming Information
Bit Name
Default
Bit No.
= 0: The receive framing pulse RSCFS and RSFSn/MRSFS are active high.
= 1: The receive framing pulse RSCFS and RSFSn/MRSFS are active low.
When the bit indicates RSCFS and MRSFS polarity, the bits of all eight framers must have the same value.
Valid when the CMS (b4, T1/J1-078H) is logic 1 and the setting in the RSCFSFALL (b1, T1/J1-003H) and that in the RSCCKRISE (b0, T1/J1-
= 0: The second active edge of RSCCK is used to update the signal on the RSDn, RSSIGn and RSFSn pins, or the first active edge of MRSCCK
= 1: The first active edge of RSCCK is used to update the signal on the RSDn, RSSIGn and RSFSn pins, or the second active edge of MRSCCK
(The signal on the RSCFS/MRSCFS pin is always sampled on the first active edge.)
In Receive Multiplexed mode, the RSD_RSCFS_EDGE in all eight framers should be set to the same value.
= 0: The bit rate of RSCCK/MRSCCK is the same as the bit rate of the backplane.
= 1: The bit rate of RSCCK/MRSCCK is double the bit rate of the backplane.
The CMS in all eight framers should be set to the same value.
Valid when the CMS (b4, T1/J1-078H) is 0.
= 0: Disable the bit offset.
= 1: Enable the bit offset.
Valid when the CMS (b4, T1/J1-078H)is ‘0’ and the BOFF_EN is ‘1’.
In Receive Clock Slave mode, when the data rate in the system side is 2.048 Mbit/s (the RSCCK2M [b4, T1/J1-001H] and RSCCK8M [b3, T1/J1-
In Receive Multiplexed mode, these bits determine the bit offset between MRSCFS and the start of the corresponding frame on MRSD and MRS-
In Receive Clock Slave mode, when the data rate in the system side is 1.544 Mbit/s, and in Receive Clock Master mode, the bit offset is disabled.
These bits define a binary number. Programming of the Bit Offsets is consistent with the convention established by the Concentration Highway
Type
Reserved
7
FPINV
R/W
6
0
RSD_RSCFS_EDGE
R/W
5
0
267
CMS
R/W
4
0
BOFF_EN
R/W
3
0
BOFF[2]
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
BOFF[1]
R/W
1
0
March 5, 2009
BOFF[0]
R/W
0
0