IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 88

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
3.14
or the data to be transmitted can be extracted to the PRBS Generator/
Detector for test in this block. The Transmit Payload Control of each
framer operates independently.
3.14.1
060H) must be set to activate the setting in the indirect registers (from
20H to 7FH of TPLC indirect registers). The following methods can be
used for test on a per-TS basis:
transmitted on one of the eight framers will be extracted to the PRBS
Generator/Detector when the RXPATGEN (b2, E1-00CH) is ‘1’. The data
can be extracted in framed or unframed mode, as determined by the
UN_DET (b0, E1-00CH). In unframed mode, all 32 time slots are
extracted and the per-timeslot configuration in the TEST (b3, E1-TPLC-
indirect registers - 20~3FH) is ignored. In framed mode, the data to be
transmitted will only be extracted on the time slot configured by the
TEST (b3, E1-TPLC-indirect registers - 20~3FH). Refer to Chapter 3.12
PRBS Generator / Detector (PRGD) for details.
indirect registers - 20~3FH) (refer to Chapter 3.23.3 Payload Loopback).
µ-law milliwatt pattern (refer to Table 8 & Table 9) when the SUBS (b7,
E1-TPLC-indirect registers - 20~3FH), the DS0 (b4, E1-TPLC-indirect
registers - 20~3FH) and the DS1 (b5, E1-TPLC-indirect registers -
20~3FH) are logic 1,1,1 or 1,1,0 respectively.
from the PRBS Generator/Detector will replace the data input from the
TSDn/MTSD pin of one of the eight framers when the RXPATGEN (b2,
E1-00CH) is ‘0’. The test pattern can replace the data in framed or
unframed mode, as determined by the UN_GEN (b1, E1-00CH). In
unframed mode, all 32 time slots are replaced and the per-timeslot con-
figuration in the TEST (b3, E1-TPLC-indirect registers - 20~3FH) is
ignored. In framed mode, the received data will only be replaced on the
time slot configured by the TEST (b3, E1-TPLC-indirect registers -
20~3FH). Refer to Chapter 3.12 PRBS Generator / Detector (PRGD) for
details.
the IDLE[7:0] (b7~0, E1-TPLC-indirect registers - 40~5FH) when the
SUBS (b7, E1-TPLC-indirect registers - 20~3FH) and the DS0 (b4, E1-
TPLC-indirect registers - 20~3FH) are logic 1,0.
pin when the SUBS (b7, E1-TPLC-indirect registers - 20~3FH), the DS0
(b4, E1-TPLC-indirect registers - 20~3FH) and the DS1 (b5, E1-TPLC-
indirect registers - 20~3FH) are logic 0,0,1 or 0,1,0 or 0,1,1 respectively.
ity.)
the A, B, C, D (b3~0, E1-TPLC-indirect registers - 61~7FH) when the
SIGSRC (b4, E1-TPLC indirect registers - 61~7FH) is logic 1 and the
Channel Associated Signaling (CAS) is chosen by the SIGEN (b6, E1-
040H) & DLEN (b5, E1-040H).
Functional Description
Different test patterns can be inserted in the data to be transmitted
To enable the test for the data to be transmitted, the PCCE (b0, E1-
- Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the data to be
- Enable the payload loopback by setting the LOOP (b2, E1-TPLC-
- Replace the data input from the TSDn/MTSD pin with the A-law or
- Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the test pattern
- Replace the data input from the TSDn/MTSD pin with the value in
- Invert the odd bits, even bits or all bits input from the TSDn/MTSD
(The above methods are arranged from highest to lowest in prior-
- Replace the signaling input from the TSSIGn pin with the value in
TRANSMIT PAYLOAD CONTROL (TPLC)
E1 MODE
78
written into the indirect registers is in the D[7:0] (b7~0, E1-063H). The
read or write operation is determined by the R/WB (b7, E1-062H). The
indirect registers have a read/write cycle. Before the read/write opera-
tion is completed, the BUSY (b7, E1-061H) will be set. New operations
on the indirect registers can only be implemented when the BUSY (b7,
E1-061H) is cleared. The read/write cycle is 490 ns.
3.14.2
J1-030H) must be set to activate the setting in the indirect registers
(from 01H to 48H of TPLC indirect registers). The following methods can
be executed for test on a per-channel basis:
be transmitted on one of the eight framers will be extracted to the PRBS
Generator/Detector when the RXPATGEN (b2, T1/J1-00FH) is ‘1’. The
data can be extracted in framed or unframed mode, as determined by
the UN_DET (b0, T1/J1-00FH). In unframed mode, all 24 channels and
the F-bit are extracted and the per-channel configuration in the TEST
(b3, T1/J1-TPLC-indirect registers - 01~18H) is ignored. In framed
mode, the data to be transmitted will only be extracted on the channel
specified by the TEST (b3, T1/J1-TPLC-indirect registers - 01~18H).
Fractional T1/J1 data can also be extracted in the specified channel
when the Nx56k_DET (b3, T1/J1-00FH) is set. Refer to Chapter 3.12
PRBS Generator / Detector (PRGD) for details.
(b1~0, T1/J1-TPLC-indirect registers - 01~18H) is configured.
TPLC-indirect registers - 01~18H) (refer to Chapter 3.23.3 Payload
Loopback).
pattern when the DMW (b5, T1/J1-TPLC-indirect registers - 01~18H) is
logic 1. (The milliwatt is µ-law. Refer to Table 9.)
tern from the PRBS Generator/Detector will replace the data input from
the TSDn pin of one of the eight framers when the RXPATGEN (b2, T1/
J1-00FH) is ‘0’. The test pattern can replace the data in framed of
unframed mode, as determined by the UN_GEN (b1, T1/J1-00FH). In
unframed mode, all 24 channels and the F-bit are replaced and the per-
channel configuration in the TEST (b3, T1/J1-TPLC-indirect registers -
01~18H) is ignored. In framed mode, the received data will only be
replaced on the channel specified by the TEST (b3, T1/J1-TPLC-indirect
registers - 01~18H). Fractional T1/J1 signal will also be replaced in the
specified channel when the Nx56k_GEN (b4, T1/J1-00FH) is set. Refer
to Chapter 3.12 PRBS Generator / Detector (PRGD) for details.
the IDLE[7:0] (b7~0, T1/J1-TPLC-indirect registers - 19~30H) when the
IDLE_DS0 (b6, T1/J1-TPLC-indirect registers - 01~18H) is set.
input from the TSDn pin when the SIGNINV and the INVERT (b4 & b7,
T1/J1-TPLC-indirect registers - 01~18H) are set.
ity.)
To enable the test for the data to be transmitted, the PCCE (b0, T1/
- Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the data to
- Enable three types of Zero Code Suppression when the ZCS[1:0]
- Enable the payload loopback by setting the LOOP (b2, T1/J1-
- Replace the data input from the TSDn/MTSD pin with the milliwatt
- Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the test pat-
- Replace the data input from the TSDn/MTSD pin with the value in
- Invert the most significant bit and/or the other bits in a channel
(The above methods are arranged from highest to lowest in prior-
Addressed by the A[6:0] (b6~0, E1-062H), the data read from or
T1/J1 MODE
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009