IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 221

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
T1 / J1 Receive Interface Configuration (003H, 083H, 103H, 183H, 203H, 283H, 303H, 383H)
MRBS:
MRBC:
complete the setting in the MRBS (b7, T1/J1-003H) before turn on this bit. This bit of the framers that are output to the same multiplexed bus must be
set to the same value.
TRI[1:0]:
RSCKRISE:
mode.
LRCKFALL:
RSCFSFALL:
Clock Slave mode and Receive Multiplexed mode.
RSCCKRISE:
MRSFS. This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode.
Programming Information
Bit Name
Default
Bit No.
Type
In Receive Multiplexed mode, this bit decides which bus the corresponding framer will use to output the received data.
= 0: The first multiplexed bus (MRSD[1], MRSFS[1], MRSSIG[1]) is selected.
= 1: The second multiplexed bus (MRSD[2], MRSFS[2], MRSSIG[2]) is selected.
This bit turns on or turn off the transmission of received data from the corresponding framer to the selected multiplexed receive bus. Users should
= 0: The corresponding framer will not output its data stream on the multiplexed bus.
= 1: The corresponding framer will output its data stream on the multiplexed bus.
These bits decide the output status of the RSDn/MRSD and RSSIGn/MRSSIG pins.
This bit selects the active edge of RSCKn to update the data on the corresponding RSDn and RSFSn.This bit is valid in Receive Clock Master
= 0: The falling edge is selected.
= 1: The rising edge is selected.
This bit selects the active edge of LRCKn to sample the data on the corresponding LRDn.
= 0: The rising edge is selected.
= 1: The falling edge is selected.
This bit selects the active edge of RSCCK/MRSCCK to sample the data on the corresponding RSCFS/MRSCFS. This bit is valid in Receive
= 0: The rising edge is selected.
= 1: The falling edge is selected.
This bit in all eight framers must be set to the same value.
This bit selects the active edge of RSCCK/MRSCCK to update the data on the corresponding RSDn/MRSD, RSSIGn/MRSSIG and RSFSn/
In the Receive Multiplexed Mode, these bits of the framers that are output to the same multiplexed bus must be set to the same value.
MRBS
R/W
7
0
TRI[1:0]
MRBC
R/W
0 0
1 0
0 1
1 1
6
0
TRI[1]
R/W
5
0
Output Status on RSDn/MRSD and RSSIGn/MRSSIG
TRI[0]
R/W
4
0
211
In high impedance
Normal operation
Reserved
Reserved
RSCKRISE
R/W
3
0
LRCKFALL
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
RSCFSFALL
R/W
1
0
March 5, 2009
RSCCKRISE
R/W
0
0