IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 70

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
3.13.1.1.2
clocked by TSCCKB. The active edge of TSCCKB used to sample the
Table 29: Active Edge Selection of TSCCKB (in E1 Transmit Clock
Slave External Signaling Mode)
Functional Description
Note:
If the FE is not equal to the DE, the active edge decided by the FE is one clock edge
before the active edge decided by the DE.
The FE (b3, E1-018H) of the eight framers should be set to the same value to ensure
TSCFS for the eight framers is sampled on the same active edge.
In this mode (refer to Figure 40), the data on the system interface is
TSSIGn
TSCFS
TSDn
TSCCKB
TSCFS
TSDn
TSSIGn
Figure 41. E1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 1
Transmit Clock Slave External Signaling Mode
TSCCKA
TSCCKB
TSCFS *
TSD[1:8] *
TSSIG[1:8] *
Note: * TSCFS, TSD, TSSIG are timed to TSCCKB
the Bit Determining the Active Edge of TSCCKB
X
1
X
2
The CMS (b2, E1-018H) is logic 0, i.e., the bankplane clock rate is 2.048Mbit/s.
Figure 40. Transmit Clock Slave External Signaling Mode
DE (b4, E1-018H)
FE (b3, E1-018H)
X
3
The DE (b4, E1-018H) is logic 0 and the FE(b3, E1-018H) is logic 1.
Transmit
Interface
X
4
System
TS31
A
5
B
6
C
7
TRANSMITTER
D
8
Generator
1
P
Frame
60
2
X
pulse on TSCFS and the data on TSDn and TSSIGn is determined by
the following bits in the registers (refer to Table 29).
each time slot is the first bit to be transmitted.
Slave mode, the special feature in this mode is that the multi-functional
pin TSFSn/TSSIGn is used as TSSIGn to input the signaling. The signal-
ing on the TSSIGn pin may replace the data on TS16 when the CCS is
disabled and the SIGSRC (b4, E1-TPLC-indirect registers - 61~7FH) in
the TPLC block is logic 0.
X
3
Figure 41 & Figure 42 show the functional timing examples. Bit 1 of
Besides all the common functions described in the Transmit Clock
X
4
(The 'X' represent the filled bits and has no meaning.)
TS0
X
5
X
6
DPLL
FIFO
X
7
X
8
1
X
2
X
T1 / E1 / J1 OCTAL FRAMER
3
X
LRCK[1:8]
LTCK[1:8]
LTD[1:8]
TS1
4
X
A
5
March 5, 2009
B
6