MK60DX256ZVLL10 Freescale Semiconductor, MK60DX256ZVLL10 Datasheet - Page 43

• Manufacturer Part Number: MK60DX256ZVLL10
• Description: KINETIS 256KFLEX ENET
• Manufacturer: Freescale Semiconductor

Specifications of MK60DX256ZVLL10

• Processor Series: K60
• Core: ARM Cortex M4
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 128 KB
• Interface Type: USB, CAN, SPI, I2C, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 2
• Number Of Timers: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: MK60DX256ZVLL10
• Supply Current (max): 185 mA
• Lead Free Status / Rohs Status: Details

6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DM3.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in
Table
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Freescale Semiconductor, Inc.
Symbol
ΔV
ΔV
V
V
C
R
V
f
f
V
ADCK
ADCK
R
REFH
REFL
ADIN
ADIN
ADIN
DDA
DDA
SSA
AS
30.
Supply voltage
Supply voltage
Ground voltage
ADC reference
voltage high
Reference
voltage low
Input voltage
Input
capacitance
Input resistance
Analog source
resistance
ADC conversion
clock frequency
ADC conversion
clock frequency
Description
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 27. 16-bit ADC operating conditions
Absolute
Delta to V
V
Delta to V
V
13/12 bit modes
f
≤ 13 bit modes
16 bit modes
Conditions
ADCK
DDA
SSA
• 16 bit modes
• 8/10/12 bit
)
)
< 4MHz
modes
DD
SS
(V
Table continues on the next page...
(V
SS
DD
-
-
Preliminary
V
V
1.71
-100
-100
1.13
Min.
Table 27
1.0
2.0
REFL
—
—
—
—
SSA
Typ.
V
V
Peripheral operating requirements and behaviors
and
—
DDA
—
—
—
—
SSA
0
0
8
4
2
1
Table 28
V
+100
+100
V
V
Max.
18.0
12.0
3.6
REFH
10
DDA
SSA
5
5
5
are achievable on the
MHz
MHz
Unit
mV
mV
pF
kΩ
kΩ
V
V
V
V
Table 29
Notes
2
2
3
4
5
and
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