MK60DX256ZVLL10 Freescale Semiconductor, MK60DX256ZVLL10 Datasheet - Page 47

• Manufacturer Part Number: MK60DX256ZVLL10
• Description: KINETIS 256KFLEX ENET
• Manufacturer: Freescale Semiconductor

Specifications of MK60DX256ZVLL10

• Processor Series: K60
• Core: ARM Cortex M4
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 128 KB
• Interface Type: USB, CAN, SPI, I2C, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 2
• Number Of Timers: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: MK60DX256ZVLL10
• Supply Current (max): 185 mA
• Lead Free Status / Rohs Status: Details

6.6.1.3 16-bit ADC with PGA operating conditions
1. Typical values assume V
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
4. For single ended configurations the input impedance of the driven input is R
5. The analog source resistance (R
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
Freescale Semiconductor, Inc.
V
Symbol
R
REFPGA
V
V
reference only and are not tested in production.
than the output of the VREF module, the VREF module must be disabled.
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
time should be allowed for F
8 MHz ADC clock.
C
V
R
PGAD
ADIN
T
DDA
rate
CM
AS
S
Supply voltage
PGA ref voltage
Input voltage
Input Common
Mode range
Differential input
impedance
Analog source
resistance
ADC sampling
time
ADC conversion
rate
Description
Table 29. 16-bit ADC with PGA operating conditions
DDA
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
in
Absolute
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
≤ 13 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
16 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
Conditions
= 3.0 V, Temp = 25°C, f
=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
AS
), external to MCU, should be kept as minimum as possible. Increased R
Preliminary
ADCK
VREF_OU
18.484
37.037
V
V
1.71
1.25
Min.
—
—
—
—
= 6 MHz unless otherwise stated. Typical values are for
SSA
SSA
T
VREF_OU
Typ.
Peripheral operating requirements and behaviors
128
100
64
32
—
—
—
—
—
—
T
1
PGAD
VREF_OU
/2
V
V
Max.
450
250
3.6
—
—
—
—
—
DDA
DDA
T
Ksps
Ksps
Unit
kΩ
µs
V
V
V
V
Ω
AS
IN+ to IN-
causes drop
Notes
2,
5
6
7
8
3
4
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