MK60DX256ZVLL10 Freescale Semiconductor, MK60DX256ZVLL10 Datasheet - Page 53

• Manufacturer Part Number: MK60DX256ZVLL10
• Description: KINETIS 256KFLEX ENET
• Manufacturer: Freescale Semiconductor

Specifications of MK60DX256ZVLL10

• Processor Series: K60
• Core: ARM Cortex M4
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 128 KB
• Interface Type: USB, CAN, SPI, I2C, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 2
• Number Of Timers: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: MK60DX256ZVLL10
• Supply Current (max): 185 mA
• Lead Free Status / Rohs Status: Details

6.6.3.2 12-bit DAC operating behaviors
1. Settling within ±1 LSB
2. The INL is measured for 0+100mV to V
3. The DNL is measured for 0+100 mV to V
4. The DNL is measured for 0+100mV to V
5. Calculated by a best fit curve from V
Freescale Semiconductor, Inc.
I
I
DDA_DACLP
t
DDA_DACH
V
Symbol
V
CCDACLP
V
t
t
PSRR
DACHP
DACLP
OFFSET
dacouth
DNL
DNL
Rop
dacoutl
T
T
INL
BW
SR
E
CT
A
P
CO
GE
G
C
Supply current — low-power mode
Supply current — high-speed mode
Full-scale settling time (0x080 to 0xF7F) — low-
power mode
Full-scale settling time (0x080 to 0xF7F) — high-
power mode
Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode and high-speed mode
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
Integral non-linearity error — high speed mode
Differential non-linearity error — V
Differential non-linearity error — V
VREF_OUT
Offset error
Gain error
Power supply rejection ratio, V
Temperature coefficient offset voltage
Temperature coefficient gain error
Offset aging coefficient
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
Channel to channel cross talk
3dB bandwidth
Description
• High power (SP
• Low power (SP
• High power (SP
• Low power (SP
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 33. 12-bit DAC operating behaviors
LP
LP
HP
HP
)
)
)
)
SS
+100 mV to V
DACR
DDA
DACR
DACR
DACR
DACR
−100 mV
> = 2.4 V
−100 mV with V
−100 mV
> 2 V
=
DACR
Preliminary
−100 mV
DDA
V
−100
0.05
Min.
550
DACR
1.2
60
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
> 2.4V
Peripheral operating requirements and behaviors
±0.4
±0.1
TBD
0.12
Typ.
100
0.7
3.7
1.7
15
—
—
—
—
—
—
—
—
—
—
—
—
V
Max.
TBD
±0.8
±0.6
150
700
200
100
250
DACR
-80
30
±8
±1
±1
90
—
—
—
—
—
—
1
ppm of
%FSR
%FSR
FSR/C
μV/yr
μV/C
V/μs
LSB
LSB
LSB
Unit
kHz
mV
mV
μA
μA
dB
dB
μs
μs
μs
Ω
Notes
1
1
1
2
3
4
5
5
6
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