MK60DX256ZVLL10 Freescale Semiconductor, MK60DX256ZVLL10 Datasheet - Page 60

• Manufacturer Part Number: MK60DX256ZVLL10
• Description: KINETIS 256KFLEX ENET
• Manufacturer: Freescale Semiconductor

Specifications of MK60DX256ZVLL10

• Processor Series: K60
• Core: ARM Cortex M4
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 128 KB
• Interface Type: USB, CAN, SPI, I2C, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 2
• Number Of Timers: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: MK60DX256ZVLL10
• Supply Current (max): 185 mA
• Lead Free Status / Rohs Status: Details

Peripheral operating requirements and behaviors
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I
6.8.5 CAN switching specifications
See
6.8.6 DSPI switching specifications (low-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
60
V
Symbol
Reg33out
C
range the maximum frequency of operation is reduced.
ESR
I
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
LIM
OUT
General switching
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
External output capacitor
External output capacitor equivalent series
resistance
Short circuit current
Description
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 41. USB VREG electrical specifications
Table 42. Master mode DSPI timing (low-speed mode)
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
specifications.
Description
(continued)
Preliminary
TBD
TBD
1.76
Min.
1
(t
(t
(t
BUS
BUS
SCK
4 x t
1.71
Min.
15
—
—
-2
4
4
0
/2) - 4
x 2) −
x 2) −
BUS
Typ.
290
2.2
—
—
(t
SCK/2)
Max.
12.5
3.6
10
—
—
—
—
—
—
Max.
TBD
8.16
100
3.6
+ 4
Freescale Semiconductor, Inc.
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
Unit
mΩ
mA
μF
V
Notes
Load
Notes
1
2
3
1
.