AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet
AD9979BCPZ
Specifications of AD9979BCPZ
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AD9979BCPZ Summary of contents
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FEATURES 1.8 V analog and digital core supply voltage Correlated double sampler (CDS) with –3 dB, 0 dB, +3 dB, and +6 dB gain 10-bit variable gain amplifier (VGA) 14-bit 65 MHz analog-to-digital converter Black-level ...
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AD9979 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications .................................................................. 4 Digital Specifications ................................................................... 5 Analog Specifications ................................................................... 6 Absolute Maximum ...
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SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE, Timing Core) RGVDD (RG, HL Drivers) HVDD ( Drivers) DVDD (Internal Digital Supply) DRVDD (Parallel Data Output Drivers ) IOVDD (I/O Supply Without the Use ...
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AD9979 TIMING SPECIFICATIONS pF, AVDD = DVDD = 1 CLI Table 2. Parameter MASTER CLOCK (CLI) CLI Clock Period CLI High/Low Pulse Width Delay from CLI Rising Edge to Internal Pixel Position 0 AFE ...
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DIGITAL SPECIFICATIONS IOVDD = 1 3.6 V, RGVDD = HVDD = 2 3 Table 3. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current ...
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AD9979 ANALOG SPECIFICATIONS AVDD = 1 MHz, typical timing specifications, t CLI Table 4. Parameter 1 CDS Allowable CCD Reset Transient CDS Gain Accuracy −3.0 dB CDS Gain 0 dB CDS Gain (Default CDS ...
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ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To AVDD AVSS DVDD DVSS DRVDD DRVSS IOVDD DVSS HVDD HVSS RGVDD RGVSS Any VSS Any VSS RG Output RGVSS H1 to H4, HL Output HVSS SCK, SL, SDI DVSS REFT, REFB, ...
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AD9979 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 7. Pin Function Descriptions Pin No. Mnemonic Type DRVSS P 7 DRVDD ...
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Pin No. Mnemonic Type 28 CLI DI 29 AVSS P 30 AVDD P 31 CCDINP AI 32 CCDINM AI 33 AVSS P 34 AVDD P 35 REFT AO 36 REFB AO 37 LDOEN SDI DI ...
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AD9979 TYPICAL PERFORMANCE CHARACTERISTICS 250 200 TOTAL POWER 150 3.3V SUPPLIES 100 50 1.8V SUPPLIES SAMPLE RATE (MHz) Figure 4. Power vs. Sample Rate 180 160 140 120 100 ...
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EQUIVALENT INPUT/OUTPUT CIRCUITS AVDD R AVSS Figure 8. CCD Input IOVDD 330Ω 100kΩ CLI + AVSS Figure 9. CLI Input, Register 0x15[0] =1 Enables the Bias Circuit AVSS DATA ENABLE Rev Page AD9979 IOVDD 330Ω ...
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AD9979 THEORY OF OPERATION V DRIVER V1 > Vx, VSG1 > VSGx, SUBCK H1 TO H4, HL D13 CCDINM/ AD9979 CCDINP CCD INTEGRATED HD, VD AFE + TD GPO1, GPO2 CLI SERIAL INTERFACE Figure 12. Typical Application ...
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PROGRAMMABLE TIMING GENERATION PRECISION TIMING HIGH SPEED TIMING CORE The AD9979 generates flexible high speed timing signals using the Precision Timing core. This core is the foundation for generating the timing for both the CCD and the AFE; the reset ...
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AD9979 PROGRAMMABLE LOCATIONS RISING EDGE FALLING EDGE RISING EDGE FALLING EDGE PROGRAMMABLE LOCATIONS: 1 ...
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Table 8. HCLK Modes (Selected by Register Address 0x23, Bits[7:5]) HCLK Mode Register Value Mode 1 001 Mode 2 010 Mode 3 100 Invalid Selection 000, 011, 101, 110, 111 Table 9. Horizontal Clock, RG, Drive, and Sample Control Registers ...
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AD9979 HORIZONTAL CLAMPING AND BLANKING The horizontal clamping and blanking pulses of the AD9979 are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK during the different regions of each field. This ...
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Table 10. CLPOB and PBLK Registers Name Length Range CLPOB0_TOG1 13 bits 0 to 8191 pixel location CLPOB0_TOG2 13 bits 0 to 8191 pixel location CLPOB1_TOG1 13 bits 0 to 8191 pixel location CLPOB1_TOG2 13 bits 0 to 8191 pixel ...
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AD9979 Individual HBLK Patterns The HBLK programmable timing shown in Figure 23 is similar to CLPOB and PBLK; however, there is no start polarity control. Only the toggle positions designate the start and the stop positions of the blanking period. ...
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Name Length Range 13 bits 0 to 8191 pixel location HBLKTOGO1 HBLKTOGO2 13 bits 0 to 8191 pixel location 13 bits 0 to 8191 pixel location HBLKTOGO3 HBLKTOGO4 13 bits 0 to 8191 pixel location HBLKTOGO5 13 bits 0 to ...
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AD9979 Increasing Horizontal Clock Width During HBLK HBLK Mode 0 and HBLK Mode 1 allow the pulse width to increase during the HBLK interval. As shown in Figure 27, the horizontal clock frequency can reduce by a ...
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HBLK Mode 2 Operation HBLK Mode 2 allows more advanced HBLK pattern operation. If unevenly spaced, multiple areas of HCLK pulses are needed; therefore, use HBLK Mode 2. Using a separate set of registers, HBLK Mode 2 can divide the ...
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AD9979 HBLK, PBLK, and CLPOB Toggle Positions The AD9979 uses an internal horizontal pixel counter to position the HBLK, PBLK, and CLPOB toggle positions. The horizontal counter does not reset to 0 until 12 CLI periods after the falling edge ...
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COMPLETE FIELD—COMBINING H-PATTERNS After creating the H-patterns, they combine to create different readout fields. A field consists nine different regions determined by the SCP registers, and within each region, a different H-pattern group can be selected, up ...
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AD9979 MODE REGISTERS To select the final field timing of the AD9979, use the mode registers. Typically, all of the field and H-pattern group information is programmed into the AD9979 at startup. During operation, the mode registers allows the user ...
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H-PATTERN MEMORY FIELD 0 FIELD 1 FIELD 2 FIELD 3 EXAMPLE 1: TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2 FIELD_SEL1 = 0 FIELD_SEL2 = 1 FIELD_SEL3 = 2 ...
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AD9979 HORIZONTAL TIMING SEQUENCE EXAMPLE Figure 34 shows an example of a CCD layout. The horizontal register contains 28 dummy pixels, which occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) ...
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GENERAL-PURPOSE OUTPUTS (GPO) The AD9979 provides programmable outputs to control a mechanical shutter, strobe/flash, the CCD bias select signal, or any other external component with general-purpose (GP) signals. Two GP signals are available, with up to two toggles each, that ...
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AD9979 Table 16. GPO Registers (Address 0x52 to Address 0x59) Name Length GP1_PROTOCOL 2 bits GP2_PROTOCOL 2 bits GP_LINE_MODE 2 bits 1 GPx_POL 2 bits GPO_OUTPUT_EN 2 bits 1 SEL_GPOx 2 bits 1 SEL_HS_GPOx 2 bits HBLK_EXT 1 bit GP_LUT_EN ...
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Single-Field Toggles Single-field toggles begin in the field following the register write. There can two toggles in the field. The mode is set with GPx_PROTOCOL equal this mode, the field toggle settings must be ...
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AD9979 ShotTimer Sequences ShotTimer technology provides internal delay of scheduled toggles. The delay is in terms of fields. Preparation The GP toggle positions can be programmed any time prior to use. For example, 0x051 ← 0x0000032 0x054 ← 0x000A001 0x055 ...
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ANALOG FRONT-END DESCRIPTION AND OPERATION DC RESTORE 1.2V SHP 1 S1 0.1µF CCDINP CDS 2 S2 CDS GAIN REGISTER PBLK NORMALLY CLOSED NORMALLY OPEN. SHP SHD PRECISION CLI GENERATION The AD9979 signal processing chain ...
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AD9979 Input Configurations The CDS circuit samples each CCD pixel twice to extract the video information and to reject the low frequency noise (see Figure 43). There are three possible configurations for the CDS: inverting CDS mode, noninverting CDS mode, ...
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SHA Mode—Differential Input Configuration In this configuration, which uses a differential input sample- and- hold amplifier (SHA), a signal is applied to the CCDINP input, while an inverse signal is applied simultaneously to the CCDINM input (see Figure 47). Sampling ...
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AD9979 Variable Gain Amplifier (VGA) The VGA stage provides a gain range of approximately dB, programmable with 10-bit resolution through the serial digital interface. A gain needed to match ...
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APPLICATIONS INFORMATION RECOMMENDED POWER-UP SEQUENCE When the AD9979 is powered up, the following sequence is recommended (refer to Figure 52 for each step). 1. Turn on the power supplies for the AD9979 and apply CLI clock. There is no required ...
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AD9979 Example Register Settings for Power-Up The following settings can be used for basic operation. A single CLPOB pulse is used with only H-pattern and one field. Additional HPATS and FIELDS can be added, as needed, along with different CLPOB ...
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VD t VDHD HD t HDCLI CLI t CLISHP SHPLOC INTERNAL SHDLOC INTERNAL HD INTERNAL 11.5 CYCLES H-COUNTER (PIXEL COUNTER) NOTES 1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, ...
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AD9979 Table 22. Standby Mode Operation I/O Block Total Shutdown (Default) AFE Off Timing Core Off H1 High-Z H2 High-Z H3 High-Z H4 High-Z HL High-Z RG High-Z 3 DOUT Low 1 To exit total shutdown, write 00 to STANDBY ...
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LDOOUT 2 VD/HD/HBLK INPUTS (LSB DRVSS 6 3V DRVDD 7 DRIVER + D5 8 SUPPLY 4.7µF 0.1µ DATA OUTPUTS NC ...
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AD9979 3-WIRE SERIAL INTERFACE TIMING All of the internal registers of the AD9979 are accessed through a 3-wire serial interface. Each register consists of a 12-bit address and a 28-bit data-word. Both the 12-bit address and the 28-bit data-words are ...
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LAYOUT OF INTERNAL REGISTERS The AD9979 address space is divided into two different register areas, as illustrated in Figure 58. In the first area, Address 0x000 to Address 0x7FF contain the registers for the AFE, miscellaneous functions, VD/HD parameters, input/output ...
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AD9979 UPDATING OF NEW REGISTER VALUES The internal registers of the AD9979 are updated at different times, depending on the register. Table 23 summarizes the three different types of register updates. The register listing tables also contain a column with ...
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COMPLETE REGISTER LISTING All addresses and default values are expressed in hexadecimal. When an address contains less than 28 data bits, all remaining bits must be written as 0s. Table 24. AFE Registers Data Bit Default Update Address Content Value ...
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AD9979 Data Bit Default Update Address Content Value Type 07 [27: [27: [27: [27: [27: [27: [ [3:1] 0 [27:4] 0E [27:0] 0F [27:0] Table 25. ...
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Table 26. VD/HD Registers Data Bit Default Update Address Content Value Type 20 [0] 0 [27:1] 21 [0] 0 SCK [2:1] 0 [27:3] 22 [27:0] 0 Table 27. I/O Control Registers Data Bit Default Update Address Content Value Type 23 ...
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AD9979 Table 29. Timing Core Registers Data Bit Default Update Address Content Value Type 30 [5:0] 0 SCK [7:6] [13:8] 20 [15:14] 0 [16] 1 [27:17] 31 [5:0] 0 SCK [7:6] [13:8] 20 [15:14] 0 [16] 1 [27:17] 32 [5:0] ...
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Data Bit Default Update Address Content Value Type 35 [2:0] 1 SCK [3] [6:4] 1 [7] [10:8] 1 [11] [14:12] 1 [15] [18:16] 1 [19] [22:20] 1 [27:23] 36 [5:0] 0 SCK [11:6] 20 [17:12] 10 [27:18] 37 [5:0] 0 ...
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AD9979 Table 30. Test Registers—Do Not Access Data Bit Default Address Content Value 3E [18:0] 4B020 [27:19] 3F [27:0] 40 [3:0] F [9:4] 0 [27:10 [27:0] Table 31. Shutter and GPIO Registers Data Default Update Address Bits ...
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Data Default Update Address Bits Value Type 53 [1: [3:2] 0 [5:4] 0 [7:6] 0 [9:8] 0 [10] 0 [27:11] 54 [3: [12:4] [25:13] 0 [27:26] 55 [12: [16:13] 0 [27:19] 56 [12:0] 0 ...
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AD9979 Table 32. Update Control Registers Data Bit Default Update Address Content Value Type 60 [15:0] 1803 SCK [27:16] 61 [15:0] E7FC SCK [27:16] 62 [15:0] F8FD SCK [27:16] 63 [15:0] 0702 SCK [27:16] 64 [15:0] FFF9 SCK [27:16] 65 ...
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Data Bit Default Update Address Content Value Type 67 [15:0] 0000 SCK [27:16 [27:0] Table 33. HPAT Registers (HPAT Registers Always Start at Address 0x800) Data Bit Default Update 1 Address Content Value Type 00 [12:0] X ...
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AD9979 Data Bit Default Update 1 Address Content Value Type 08 [2:0] X SCP [5:3] X [8:6] X [11:9] X [14:12] X [17:15] X [19:18] X [20] X [27:21] 09 [12:0] X SCP [20:13] X [21] X [22] X [27:23] ...
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Data Bit Default Update 1 Address Content Value Type 04 [12: [27:13] 05 [4: [9:5] X [14:10] X [19:15] X [24:20] X [27:25] 06 [4: [9:5] X [14:10] X [19:15] X [27:20] 07 [27:0] ...
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... OUTLINE DIMENSIONS BSC SQ PIN 1 INDICATOR VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9979BCPZ −25°C to +85°C AD9979BCPZRL −25°C to +85° RoHS Compliant Part. 7.00 0.60 MAX 0.60 MAX 37 36 TOP 6.75 BSC SQ 0.50 0. 0.30 ...
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NOTES Rev Page AD9979 ...
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AD9979 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05957-0-10/09(C) Rev Page ...