AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 17

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10. CLPOB and PBLK Registers
Name
CLPOB0_TOG1
CLPOB0_TOG2
CLPOB1_TOG1
CLPOB1_TOG2
CLPOB_POL
CLPOB_PAT
CLPOBMASKSTARTx
CLPOBMASKENDx
PBLK0_TOG1
PBLK0_TOG2
PBLK1_TOG1
PBLK1_TOG2
PBLK_POL
PBLK_PAT
PBLKMASKSTARTx
PBLKMASKENDx
HBLK
H1/H3
HBLK
HD
HD
H1/H3
H2/H4
HBLKTOGE1
Length
13 bits
13 bits
13 bits
13 bits
9 bits
9 bits
13 bits
13 bits
13 bits
13 bits
13 bits
13 bits
9 bits
9 bits
13 bits
13 bits
BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 (HBLKALT_PATx = 0).
BLANK
Range
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
High/low
0 to 9 settings
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
High/low
0 to 9 settings
0 to 8191 pixel location
0 to 8191 pixel location
HBLKTOGE2
Figure 23. Typical Horizontal Blanking Pulse Placement (HBLKMODE = 0)
THE POLARITY OF H1/H3 DURING BLANKING IS PROGRAMMABLE
(H2/H4 AND HL POLARITIES ARE SEPARATELY PROGRAMMABLE).
Figure 24. HBLK Masking Control
Rev. C | Page 17 of 56
Description
First CLPOB0 toggle position within the line for each V-sequence.
Second CLPOB0 toggle position within the line for each V-sequence.
First CLPOB1 toggle position within the line for each V-sequence.
Second CLPOB1 toggle position within the line for each V-sequence.
Starting polarity of CLPOB for each V-sequence[8:0] (in field registers).
CLPOB pattern selection for each V-sequence[8:0] (in field registers).
CLPOB mask start position. Three values available (in field registers).
CLPOB mask end position. Three values available (in field registers).
First PBLK0 toggle position within the line for each V-sequence.
Second PBLK0 toggle position within the line for each V-sequence.
First PBLK1 toggle position within the line for each V-sequence.
Second PBLK1 toggle position within the line for each V-sequence.
Starting polarity of PBLK for each V-sequence[8:0] (in field registers).
PBLK pattern selection for each V-sequence[8:0] (in field registers).
PBLK mask start position. Three values available (in field registers).
PBLK mask end position. Three values available (in field registers).
BLANK
AD9979