AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 30

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
ShotTimer Sequences
ShotTimer technology provides internal delay of scheduled
toggles. The delay is in terms of fields.
Preparation
The GP toggle positions can be programmed any time prior to
use. For example,
Details
GP1_PROTOCOL 0
GP LOOK-UP TABLES (LUT)
The AD9979 includes a LUT for each pair of consecutive GP
signals when configured as outputs. The external GPO outputs
from the GPO1 pair can output the result of the LUT or the
original GPO internal signal.
0x051 ← 0x0000032
0x054 ← 0x000A001
0x055 ← 0x0004000
0x056 ← 0x000000F
0x052 ← 0x0000002
A) Field 0: 0x050 ← 0x0000003
REG WRITE
GP1_INT
GP2_INT
Figure 39. ShotDelay Toggle Operation Using GP1_PROTOCOL = 3
PRIMARY
COUNT
GPO1
VD
Figure 40. Internal LUT for GPO1 and GPO2 Signals
0 (IDLE)
A
3
1
1
LUT
2
2
3
GP_LUT_EN [8]
GP_LUT_EN [9]
3
0
1
0
1
1
GPO1
GPO2
4
2
5
0
Rev. C | Page 30 of 56
Address 0x52 dictates the behavior of the LUT and identifies
which signals receive the result. Each 4-bit register can realize
any logic combination of GPO1 and GPO2. Table 17 shows
how the register values of GP12_LUT[13:10] are determined.
XOR, NAND, AND, and OR results are shown, but any 4-bit
combination is possible. A simple example of XOR gating is
shown in Figure 41.
Table 17. LUT Results Based on GPO1, GPO2 Values
GPO2
0
0
1
1
Field Counter and GPO Limitations
1.
2.
3.
GP1_INT
GP2_INT
GPO2
GPO1
The following is a summary of the known limitations of the
field counters and GPO signals that dictate usability.
The field counter trigger (Address 0x50) is self-reset at the
start of every VD period. Therefore, there must be one VD
period between sequential programming to that address.
If the protocol is set to 1, the toggles repeat for each field
until the protocol is set to idle.
LOGIC COMBINATION (XOR) OF PROGRAMMED TOGGLES
GPO1 AND GPO2.
GPO1
0
1
0
1
Figure 41. LUT Example for GPO1 XOR GPO2
XOR
0
1
1
0
GP12_LUT = 0x6
GP_LUT_EN = 0x2
NAND
1
1
1
0
LUT
AND
0
0
0
1
OR
0
1
1
1