AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 26

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 34 shows an example of a CCD layout. The horizontal
register contains 28 dummy pixels, which occur on each line
clocked from the CCD. In the vertical direction, there are 10 optical
black (OB) lines at the front of the readout and 2 OB lines at the
back of the readout. The horizontal direction has 4 OB pixels in
the front and 48 in the back.
Figure 35 shows the basic sequence layout to use during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.
Because PBLK is used to isolate the CDS input (see the Analog
Front-End Description and Operation section), the PBLK signal
cannot be used during CLPOB operation. The change in the
offset behavior that occurs during PBLK impacts the accuracy
of the CLPOB circuitry.
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers. More elaborate clamping schemes can
be used, such as adding in a separate sequence to clamp in the
entire shield OB lines. This requires configuring a separate
V-sequence for clocking out the OB lines.
The CLPOB mask registers are also useful for disabling the
CLPOB on a few lines without affecting the setup of the
CCD OUTPUT
CLPOB
H1/H3
H2/H4
HBLK
PBLK
SHP
SHD
HD
NOTES
1. IT IS RECOMMENDED THAT PBLK ACTIVE (LOW) NOT BE USED DURING CLPOB ACTIVE (LOW).
OB
VERTICAL SHIFT
DUMMY
Figure 35. Horizontal Sequence Example
OB
Rev. C | Page 26 of 56
EFFECTIVE PIXELS
clamping sequences. It is important to use CLPOB only during
valid OB pixels. During other portions on the frame timing, such
as during vertical blanking or SG line timing, the CCD does not
output valid OB pixels. Any CLPOB pulses that occur during this
time cause errors in clamping operation, and therefore, cause
changes in the black level of the image.
28 DUMMY PIXELS
4 OB PIXELS
V
Figure 34. Example CCD Configuration
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
H
OB
48 OB PIXELS
VERT. SHIFT
10 VERTICAL
OB LINES
2 VERTICAL
OB LINES