AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 31

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ANALOG FRONT-END DESCRIPTION AND OPERATION
The AD9979 signal processing chain is shown in Figure 42.
Each processing step is essential in achieving a high quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.2 V, to be compatible with the 1.8 V core
supply voltage of the AD9979. The dc restore switch is active
during the SHP sample pulse time.
The dc restore circuit can be disabled when the optional PBLK
signal is used to isolate large signal swings from the CCD input
(see the Analog Preblanking section). Bit 6 of Address 0x00
controls whether the dc restore is active during the PBLK interval
(see Table 24).
Analog Preblanking
During certain CCD blanking or substrate clocking intervals,
the CCD input signal to the AD9979 can increase in amplitude
beyond the recommended input range. The PBLK signal can
be used to isolate the CDS input from large signal swings. As
shown in Figure 42, when PBLK is active (low), the CDS input
is isolated from the CCDINx pin (S1 open) and is internally
shorted to ground (S2 closed).
0.1µF
CCDINP
CLI
1.2V
PBLK
1
2
S1 IS NORMALLY CLOSED.
S2 IS NORMALLY OPEN.
S1
DC RESTORE
1
S2
2
SHP SHD
REGISTER
CDS GAIN
GENERATION
SHP
CDS
PRECISION
TIMING
SHD
–3dB, 0dB,
+3dB, +6dB
SHP
PBLK (WHEN DCBYP = 1)
PHASE
DOUT
Figure 42. Analog Front End Functional Block Diagram
REGISTER
VGA GAIN
6dB TO 42dB
VGA
CLPOB PBLK
GENERATION
Rev. C | Page 31 of 56
TIMING
V-H
DAC
During the PBLK active time, the ADC outputs can be pro-
grammed to output all zeros or the programmed clamp level.
Note that because the CDS input is shorted during PBLK, the
CLPOB pulse must not be used during the same active time as
the PBLK pulse.
Correlated Double Sampler (CDS)
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject low frequency noise. The
timing shown in Figure 19 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and to sample the CCD signal level, respectively.
The placement of the SHP and SHD sampling edges is deter-
mined by the setting of the SHPLOC and SHDLOC registers,
located at Address 0x36. Placement of these two clock signals is
critical in achieving the best performance from the CCD.
The CDS gain is variable in four steps, set by using CDSGAIN
(Address 0x04): −3 dB, 0 dB (default), +3 dB, and +6 dB (see
Table 24). Improved noise performance results from using the
+3 dB and +6 dB settings, but the input range is reduced with
these settings (see Table 4).
DIGITAL
FILTER
OPTICAL BLACK
INTERNAL
CLAMP
0.1µF 0.1µF
REFB
0.4V
14-BIT
V
ADC
REF
2V FULL SCALE
CLAMP-LEVEL
REFT
1.4V
REGISTER
CLPOB
DOUT PHASE
OUTPUT
LATCH
DATA
PBLK
BLANK TO
ZERO OR
CLAMP LEVEL
AD9979
14
DOUT
VD
HD
D0 TO D13
AD9979