AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 32

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
Input Configurations
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject the low frequency noise (see
Figure 43). There are three possible configurations for the CDS:
inverting CDS mode, noninverting CDS mode, and SHA mode.
CDSMODE (Address 0x00[9:8]) selects which configuration is
used (see Table 24).
Inverting CDS Mode
For this configuration, the signal from the CCD is applied
to the positive input of the CDS system (CCDINP) and the
negative side (CCDINM) is grounded (see Figure 44). The
CDSMODE setting for this configuration is 0x00. Traditional
CCD applications use this configuration with the reset level
established below the AVDD supply level, by the AD9979 dc
restore circuit, at approximately 1.5 V. The maximum saturation
level is 1.0 V below the reset level, as shown in Figure 45 and
Table 18. A maximum saturation voltage of 1.4 V is also
possible when using the minimum CDS gain setting.
CCDINM
CCDINP
NOTES
1. COUPLING CAPACITOR IS NOT REQUIRED FOR CERTAIN
BLACK-LEVEL REFERENCE VOLTAGES.
SENSOR
IMAGE
Figure 43. CDS Block Diagram (Conceptual)
Figure 44. Single-Input CDS Configuration
SHA1
SHA2
SHP
SHD
CCDINM
CCDINP
DIFF
AMP
SHA/
CDS
AD9979
CDS OUTPUT
Rev. C | Page 32 of 56
RESET LEVEL
Table 18. Inverting Voltage Levels
Signal Level
Saturation
Reset
Supply Voltage
Noninverting CDS Mode
If the noninverting input is desired, the reset level signal (or black
level signal) is established at a voltage above ground potential.
Saturation level (or white level) is approximately 1 V. Samples are
taken at each signal level (see Figure 46 and Table 19).
RESET LEVEL
Table 19. Noninverting Voltage Levels
Signal Level
Saturation
Reset
(V
(V
RST
RST
)
)
V
GND
DD
(N) RESET SAMPLE
(N) RESET SAMPLE
Figure 45. Traditional Inverting CDS Signal
Figure 46. Noninverting CDS Signal
Symbol
V
V
V
Symbol
V
V
FS
RST
DD
FS
RST
SIGNAL LEVEL
(N) SIGNAL SAMPLE
SIGNAL LEVEL
(N) SIGNAL SAMPLE
Min
V
1600
DD
(V
Min
0
(V
− 500
FS
FS
)
)
Typ
1000
250
Typ
1000
V
1800
DD
− 300
(N + 1) RESET SAMPLE
(N + 1) RESET SAMPLE
Max
1400
500
Max
1400
V
2000
DD
Unit
mV
mV
Unit
mV
mV
mV