AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 15

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8. HCLK Modes (Selected by Register Address 0x23, Bits[7:5])
HCLK Mode
Mode 1
Mode 2
Mode 3
Invalid Selection
Table 9. Horizontal Clock, RG, Drive, and Sample Control Registers Parameters
Name
Polarity
Positive Edge
Negative Edge
Sample Location
Drive Control
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9979
features on-chip output drivers for the HL, RG, and H1 to H4
outputs. These drivers are powerful enough to directly drive
the CCD inputs. The H-driver and RG-driver currents can be
adjusted for optimum rise/fall times into a particular load by
using the drive strength control register (Address 0x35). Use
the register to adjust the drive strength in 4.3 mA increments.
The minimum setting of 0 is equal to off or three-state, and the
maximum setting of 7 is equal to 30.1 mA.
DOUTPHASE
NOTES
1. EXAMPLE SHOWN FOR SHDLOC = 0.
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
(INTERNAL)
(INTERNAL)
ADC OUT
CCDIN
DOUT
SHD
CLK
CLI
t
CLIDLY
N–17
N–17
N
Length
1 bit
6 bits
6 bits
6 bits
3 bits
Register Value
001
010
100
000, 011, 101, 110, 111
SAMPLE PIXEL N
N–16
N+1
N–16
t
DOUTINH
N–15
N+2
N–15
Range
High/low
0 to 63 edge location
0 to 63 edge location
0 to 63 sample location
0 to 7 current steps
N–14
N+3
N–14
N–13
N+4
N–13
N–12
Figure 20. Pipeline Delay of AFE Data Outputs
N+5
N–12
N–11
N+6
N–11
Description
H1 edges are programmable; H3 = H1, H2 = H4 = inverse of H1.
H1 edges are programmable; H3 = H1.
H2 edges are programmable; H4 = H2.
H1 edges are programmable; H2 = inverse of H1.
H3 edges are programmable; H4 = inverse of H3.
Invalid register settings.
PIPELINE LATENCY = 16 CYCLES
Rev. C | Page 15 of 56
N–10
N+7
N–10
Description
Polarity control for H1/H3 and RG; 0 = no inversion, 1 = inversion
Negative edge location for H1/H3 and RG
Sampling location for SHP and SHD
Positive edge location for H1/H3 and RG
Drive current for H1 to H4 and RG outputs (4.3 mA steps)
N–9
N+8
N–9
N–8
N+9
Digital Data Outputs
For maximum system flexibility, the AD9979 uses DOUTPHASEN
and DOUTPHASEP (Address 0x37, Bits[11:0]) to select the
location for the start of each new pixel data value. Any edge
location from 0 to 63 can be programmed. Register 0x37
determines the start location of the data output and the
DOUTPHASEx clock rising edge with respect to the master
clock input CLI.
The pipeline delay through the AD9979 is shown in Figure 20.
After the CCD input is sampled by SHD, there is a 16-cycle
delay before the data is available.
N–8
N+10
N–7
N–7
N–6
N+11
N–6
N+12
N–5
N–5
N+13
N–4
N–4
N+14
N–3
N–3
N+15
N–2
N–2
N+16
N–1
N–1
N+17
N
N
N+1
AD9979
N+1