AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 47

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Address
35
36
37
38
39
3A
3B
3C
3D
1
2
3
Recommended setting is enable retime. Enabling retime adds one cycle delay to programmed HBLK positions.
See Address 34, Bit 0 for setting options.
See Address 35, Bits[2:0] for setting options.
Data Bit
Content
[2:0]
[3]
[6:4]
[7]
[10:8]
[11]
[14:12]
[15]
[18:16]
[19]
[22:20]
[27:23]
[5:0]
[11:6]
[17:12]
[27:18]
[5:0]
[11:6]
[12]
[14:13]
[15]
[27:16]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
Default
Value
1
1
1
1
1
1
0
20
10
0
20
0
2
0
Update
Type
SCK
SCK
SCK
Name
H1DRV
Unused
H2DRV
Unused
H3DRV
Unused
H4DRV
Unused
HLDRV
Unused
RGDRV
Unused
SHDLOC
SHPLOC
SHPWIDTH
Unused
DOUTPHASEP
DOUTPHASEN
DCLKMODE
CLKDATA_SEL
INV_DCLK
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Rev. C | Page 47 of 56
Description
H1 drive strength.
0 = off.
1 = 4.3 mA.
2 = 8.6 mA.
3 = 12.9 mA.
4 = 17.2 mA.
5 =21.5 mA.
6 = 25.8 mA.
7 = 30.1 mA.
Set unused bits to 0.
H2 drive strength.
Set unused bits to 0.
H3 drive strength.
Set unused bits to 0.
H4 drive strength.
Set unused bits to 0.
HL drive strength.
Set unused bits to 0.
RG drive strength.
Set unused bits to 0.
SHD sampling edge location.
SHP sampling edge location.
SHP width. Controls input dc restore switch active time.
Set unused bits to 0.
DOUT positive edge phase control.
DOUT negative edge phase control. Set DOUTPHASEN =
DOUTPHASEP + 0x20.
0 = DCLK tracks DOUT phase.
1 = DCLK is CLI post-Schmitt trigger and postdivider when CLIDIVIDE = 1.
Data output clock selection.
0 = no delay.
1 = ~4 ns.
2 = ~8 ns.
3 =~12 ns.
0 = no inversion.
1 = invert DCLK to output.
Set unused bits to 0.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
3
3
3
3
3
AD9979