AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 20

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
Increasing Horizontal Clock Width During HBLK
HBLK Mode 0 and HBLK Mode 1 allow the H1 to H4 pulse width
to increase during the HBLK interval. As shown in Figure 27,
the horizontal clock frequency can reduce by a factor of 1/2,
1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30 (see Table 12). To
enable this feature, the HCLK_WIDTH register (Address 0x34,
Bits[7:4]) is set to a value between 1 and 15. When this register
is set to 0, the wide HCLK feature is disabled.
Table 12. HCLK Width Register
Name
HCLK_WIDTH
HBLK
H1/H3
H2/H4
Length
4 bits
Figure 27. Generating Wide Horizontal Clock Pulses During HBLK Interval
1/
f
PIX
HORIZONTAL CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLK_WIDTH REGISTER.
Description
Controls H1 to H4 width during HBLK as a fraction of pixel rate.
0 = same frequency as pixel rate
1 = 1/2 pixel frequency, that is, doubles the HCLK pulse width
2 = 1/4 pixel frequency
3 = 1/6 pixel frequency
4 = 1/8 pixel frequency
5 = 1/10 pixel frequency
6 = 1/12 pixel frequency
7 = 1/14 pixel frequency
8 = 1/16 pixel frequency
9 = 1/18 pixel frequency
10 = 1/20 pixel frequency
11 = 1/22 pixel frequency
12 = 1/24 pixel frequency
13 = 1/26 pixel frequency
14 = 1/28 pixel frequency
15 = 1/30 pixel frequency
Rev. C | Page 20 of 56
2 × (1/
f
PIX
)
The reduced frequency occurs only for H1 to H4 pulses that are
located within the HBLK area.
The HCLK_WIDTH feature is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Note that the wide HCLK feature is available only in HBLK
Mode 0 and HBLK Mode 1, and not in HBLK Mode 2.