AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 33

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SHA Mode—Differential Input Configuration
In this configuration, which uses a differential input sample-
and- hold amplifier (SHA), a signal is applied to the CCDINP
input, while an inverse signal is applied simultaneously to the
CCDINM input (see Figure 47). Sampling occurs on both
signals at the same time, creating the differential output for
amplification and for the ADC (see Figure 48 and Table 20).
BLACK SIGNAL LEVEL (V
Table 20. SHA Mode—Differential Voltage Levels
Signal Level
Black Signal Level
Saturation Signal
Minimum Signal
SHA Mode—DC-Coupled, Single-Ended Input
The SHA mode can also be used in a single-ended fashion,
with the signal from the image sensor applied to the CDS/SHA
using a single input, CCDINP. This is similar to the differential
configuration, except in this case, the CCDINM line is held at a
constant dc voltage. This establishes a reference level that matches
the image sensor reference voltage (see Figure 49).
Referring to Figure 50 and Table 21, the CCDINM signal is a
constant dc voltage set at a level above ground potential. The
sensor signal is applied to the other input, and samples are
taken at the signal minimum and at a point of signal maximum.
The resulting differential signal is the difference between the
signal and the reference voltage.
Level
Level
GND
(N) SIGNAL SAMPLE
Figure 47. SHA Mode—Differential Input Configuration
SENSOR
IMAGE
Figure 48. SHA Mode—Differential Input Signal
MINIMUM SIGNAL LEVEL (V
BLK
V
V
V
Symbol
BLK
FS
MIN
)
(N + 1) SIGNAL SAMPLE
PEAK SIGNAL
LEVEL (V
CCDINM
CCDINP
1000
0
Min
MIN
FS
)
Typ
0
V
1800
)
DD
SHA/
CDS
− 300
AD9979
POSITIVE INPUT
NEGATIVE INPUT
Max
1400
mV
mV
mV
Unit
Rev. C | Page 33 of 56
NOTES
1. DC VOLTAGE ABOVE GROUND CAN BE USED TO
Table 21. SHA Mode—Single-Ended, Input Voltage Levels
Signal Level
Black Signal Level
Saturation Signal Level
Minimum Signal Level
CDS Timing Control
The timing shown in Figure 19 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and the data level of the CCD signal, respectively.
The placement of the SHP and SHD sampling edges is determined
by the setting of SHPLOC and SHDLOC, located at Address 0x36.
Placement of these two clock signals is critical in achieving the
best performance from the CCD.
SHA Timing Control
When SHA mode is selected, only the SHPLOC setting is used
to sample the input signal, but the SHDLOC signal still needs to
be programmed to an edge setting of SHPLOC + 32.
BLACK SIGNAL LEVEL (V
MATCH THE SENSOR REFERENCE LEVEL.
Figure 49. SHA Mode—DC-Coupled, Single-Ended Input Configuration
SENSOR
GND
IMAGE
Figure 50. SHA Mode—DC-Coupled, Single-Ended Input Signal
(N) SIGNAL SAMPLE
MINIMUM SIGNAL LEVEL (V
BLK
)
CCDINM
CCDINP
Symbol
V
V
V
BLK
FS
MIN
(N + 1) SIGNAL SAMPLE
PEAK SIGNAL
LEVEL (V
SHA/
CDS
MIN
0
Min
AD9979
FS
)
)
Typ
0
1000
POSITIVE INPUT
NEGATIVE INPUT
Max
1400
AD9979
Unit
mV
mV
mV