AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet
AD9898KCP-20
Specifications of AD9898KCP-20
Related parts for AD9898KCP-20
AD9898KCP-20 Summary of contents
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FEATURES Correlated Double Sampler (CDS Variable Gain Amplifier (VGA) Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with 1 ns Resolution On-Chip: 2-Channel Horizontal and 1-Channel RG Drivers 2-Phase ...
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AD9898 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD (H1–H2 Drivers) DRVDD (Data Output Drivers) DVDD (Digital) POWER DISSIPATION 20 MHz, Typical Supply Levels, 100 pF H1–H2 ...
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AD9898 ANALOG SPECIFICATIONS Parameter CDS Allowable CCD Reset Transient Maximum Input Range before Saturation* 1.0 Maximum CCD Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Maximum Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain Maximum Gain BLACK LEVEL ...
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TIMING SPECIFICATIONS Parameter MASTER CLOCK, CLI CLI Clock Period CLI High/Low Pulsewidth Delay from CLI Rising Edge to Internal Pixel Position 0 AFE CLAMP PULSES* CLPOB Pulsewidth AFE SAMPLE LOCATION* (See Figure 13) SHP Sample Edge to SHD Sample Edge ...
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... PACKAGE THERMAL CHARACTERISTICS Thermal Resistance = 92°C/W JA Model Temperature Range AD9898KCP-20 –20ºC to +85ºC AD9898KCPRL-20 –20ºC to +85ºC CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9898 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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Pin No. Mnemonic Type* Description Data Output Data Output Data Output Data Output Data Clock Output 6 DRVSS P Data Output Driver Ground 7 DRVDD ...
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AD9898 SPECIFICATION DEFINITIONS Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit ...
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V = 3.3V DD 140 V = 3.0V DD 120 100 SAMPLE RATE – MHz TPC 1. Power vs. Sample Rate REV. 0 Typical Performance Characteristics–AD9898 0.3 0.15 0 –0.15 ...
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AD9898 Table I. Control Register Address Map (Register Names Are Subject to Change) Bit Default Address Content Width Value 00 (23:0) 23 000000 01 (23:21 (19:18 (15:14) ...
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Table I. Control Register Address Map (Register Names Are Subject to Change) Bit Default Address Content Width Value (21:16) 6 0x00 (15:12 (VD (11:10 SyncReg ...
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AD9898 Bit Default Register Content Width (Decimal) Register Name Sys_Reg(0) (31:24 (23: Sys_Reg(1) (31:23 (18:10 (9: ...
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Table II. System Register Address Map (Addr 0x14) (continued) Bit Default Register Content Width (Decimal) Register Name Sys_Reg(9) (31:23 (18:10 (9: ...
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AD9898 Bit Default Register Content Width (Decimal) Register Name Mode_Reg(0) (31:24 (23: Mode_Reg(1) (31:21) 11 262 (20:9) 12 1139 (6: Mode_Reg( (30:28 (27:25) ...
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Bit Default Register Content Width (Decimal) Register Name Mode_Reg(0) (31:24 (23: Mode_Reg(1) (31:21) 11 262 (20:9) 12 1139 (6: Mode_Reg( (30:28 (27:25) 3 ...
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AD9898 SYSTEM OVERVIEW Figure 5 shows the typical system block diagram for the AD9898. The CCD output is processed by the AD9898’s AFE circuitry, which consists of a CDS, VGA, black level clamp, and A/D converter. The digitized pixel information ...
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SERIAL INTERFACE TIMING All of the internal registers of the AD9898 are accessed through a 3-wire serial interface. The interface consists of a clock (SCK), serial load (SL), and serial data (SDATA). The AD9898 has three different register types that ...
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AD9898 ADDRESS [7:0] NUMBER WRITES N [23:0] SDATA 8-BIT ADDRESS SCK SL 1. ALL SL PULSES ARE IGNORED UNTIL THE LSB OF THE LAST DATA N WORD IS CLOCKED IN. 2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ...
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ANALOG FRONT END (AFE) DESCRIPTION AND OPERATION The AD9898 AFE signal processing chain is shown in Figure 10. Each processing step is essential to achieving a high quality image from the raw CCD pixel data. Registers for the AD9898 AFE ...
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AD9898 H-Driver and RG Outputs In addition to the programmable timing positions, the AD9898 features on-chip output drivers for the RG and H1–H2 outputs. They are sufficiently powerful to directly drive the CCD inputs. The H-driver current can be adjusted ...
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Table VIII. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters Register Name Bit Width RGNEGLOC 6 H1POSLOC 6 SHPLOC 6 SHDLOC 6 DOUTPHASE 6 DCLKPHASE 6 The 2 MSB are used to select the quadrant. Table IX. Precision Timing ...
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AD9898 P[0] POSITION PIXEL PERIOD RGr[0] RG Hr[0] H1 cds (INTERNAL) CCD SIGNAL 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. 2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. Figure 13. ...
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EXTERNAL SYNCHRONIZATION (MASTER MODE) External synchronization can be used to synchronize the VD and HD signal by applying an external pulse on the SYNC/ VGATE pin (Pin 45) for master mode operation. The SYNC/ VGATE pin is configured as an ...
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AD9898 HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING The HD and VD output pulses are programmable using the registers listed in Table XI. The HD output is asserted low at the start of the horizontal line shift. The VD output is asserted ...
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Register Bit Name Width Register Type CLP_CONT 1 Control (0x01) CLP_MODE 1 Control(0x01) CLPTOG1 12 Sys_Reg(15) CLPTOG2 12 Sys_Reg(15 and 16) HD CLPEN0 1 Mode_Reg(2) CLPEN1 1 Mode_Reg(2) CLPEN2 1 Mode_Reg(2) CLPEN3 1 Mode_Reg(2) CLPEN4 1 Mode_Reg( 12-BIT ...
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AD9898 Controlling CLPOB Clamp Pulse Outputs The registers in Table XII are used for programming the CLPOB pulse, which will be disabled in all CCD regions by setting CLPCNT = 0. The CLPTOGx ( are used to ...
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H1 AND H2 BLANKING The AD9898 provides three options for controlling the period where H1 and H2 pulses get blanked. These options are normal H blanking, selective positioning for 2 H1 and H2 outputs, and extended blanking. In all cases, ...
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AD9898 HD HBLK (INTERNAL) H12 (INTERNAL THE H2 POLARITY IS OPPOSITE THE POLARITY OF H1. Figure 24. Selective H-Blanking Operation HBLKMASK = 0, HPULSECNT = 1, HBLKHPOS = 003 BLLEN 9-BIT BL COUNTER CLPOB 1. ...
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VGATE MASKING OF V1–V4 AND CLPOB OUTPUTS During slave mode operation, the SYNC/VGATE, Pin 45, is configured as an input for an external VGATE signal. While operating in this mode, the external VGATE signal can be used to mask the ...
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AD9898 VERTICAL TIMING GENERATION The AD9898 provides a very flexible solution for generating vertical CCD timing and can support multiple CCDs and dif- ferent system architectures. The 4-phase vertical transfer clocks V1–V4 are used to shift each line of pixels ...
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VTPLENx [8:0] = 210 Figure 29. Step 2: Create Individual Sequences for V1–V4 Outputs by Assigning Pulse Repetitions to VTP0, VTP1, VTP2, and VTP3 Patterns. This ...
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AD9898 Table XV. V1–V4 Registers to Configure V1–V4 Pulse for Each VTP Pattern Register Bit Register Name Width Type VTPLEN0 9 Sys_Reg(1) V1STARTPOL0 1 Sys_Reg(1) V2STARTPOL0 1 Sys_Reg(1) V3STARTPOL0 1 Sys_Reg(1) V4STARTPOL0 1 Sys_Reg(1) V1TOG1POS0 9 Sys_Reg(1) V1TOG2POS0 9 Sys_Reg(1) ...
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Table XVI. Mode_A and Mode_B Registers for VTPx Selection Register Bit Register Name Width Type VTPSEQPTR0* 3 Mode_Reg(2) VTPSEQPTR1* 3 Mode_Reg(2) VTPSEQPTR2* 3 Mode_Reg(2) VTPSEQPTR3* 3 Mode_Reg(2) VTPSEQPTR4* 3 Mode_Reg(2) VTPSEL0 2 Mode_Reg(3) VTPSEL1 2 Mode_Reg(3) VTPSEL2 2 Mode_Reg(3) VTPSEL3 ...
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AD9898 Special Vertical Sweep Mode Operation The AD9898 contains a special mode of vertical timing operation called sweep mode. This mode is used to generate a continu- ous number of repetitive vertical pulses that span multiple HD lines. One example ...
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Register Bit Name Width Register Type SPAT_EN 1 Control (Addr 0x0A) SPATLOGIC 4 Control (Addr 0x0A) V1SPAT_TOG1 13 Mode_Reg(5) V1SPAT_TOG2 13 Mode_Reg(5) V2SPAT_TOG1 13 Mode_Reg(6) V2SPAT_TOG2 13 Mode_Reg(6) V3SPAT_TOG1 13 Mode_Reg(6 and 7) V3SPAT_TOG2 13 Mode_Reg(7) V4SPAT_TOG1 13 Mode_Reg(7) V4SPAT_TOG2 ...
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AD9898 VD HD 13-BIT ST COUNTER (FIXED) INTERNAL V1 WITHOUT SPAT APPLIED INTERNAL SPAT TIMING FOR V1 WITH SPATLOGIC = 0 V1 OUTPUT WITH SPAT APPLIED VSGx 1. THE VxSPAT_TOG1 AND VxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER. 2. THE ...
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Bit Register Name Width Register Type SUBCKNUM 11 Control (Addr 0x0B) SUBCKSUPPRESS 1 Control (Addr 0x01) SUBCK_EN 1 Control (Addr 0x0B) SUBCKMODE_HP 1 Control (Addr 0x01) SUBCKNUM_HP 3 Control (Addr 0x0B) SUBCK1TOG1 9 System_Reg(14) SUBCK1TOG2 9 System_Reg(14) SUBCK2TOG1 9 System_Reg(15) ...
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AD9898 VD HD VSG1– VSG2 1 SUBCK 2 3 SUBCK PROGRAMMABLE SETTINGS 1. SUBCK STARTING POLARITY IS ALWAYS HIGH. 2. FALLING EDGE OF SUBCK IS SET USING THE SUBCK1TOG1 OR SUBCK2TOG1 REGISTERS. 3. RISING EDGE OF SUBCK IS SET USING ...
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HD OLEN 9-BIT OL-COUNTER SUBCK NORMAL SHUTTER MODE PULSE ALWAYS OUTPUT HD 9-BIT OL-COUNTER SUBCK Figure 40. Electronic Shutter Timing Example with SUBCKMODE_HP = 0 and SUBCKNUM_HP = 1 HD 9-BIT OL-COUNTER SUBCK Figure 41. Electronic Shutter Timing Example with ...
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AD9898 VSG TIMING The VSG timing is controlled using the registers in Table XXIII. Two unique preprogrammed VSG pulses can be configured using the VSGTOG1_x ( registers. As shown in Figure 42, the period of the VSG ...
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VSUB CONTROL The CCD readout bias (VSUB) can be programmed to accom- modate different CCDs. VSUB ON and OFF toggle positions and polarity are controlled using VSUBTOG (Addr 0x0D) and VSUBPOL (Addr 0x0D) registers, respectively, as described in Table XXIV. ...
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AD9898 MSHUT CONTROL MSHUT Basic Operation The AD9898 provides an MSHUT output pulse that can be configured to control the mechanical shutter of the camera. The registers used to control the MSHUT pulse are listed in Table XXV. The MSHUT ...
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MSHUT High Precision Operation The MSHUTPOS_HP register allows more precise control of the MSHUT position within a line. Under normal MSHUT operation when MSHUTPOS_HP = 0, the MSHUT polarity changes from high to low on the negative edge of the ...
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AD9898 STROBE Control The AD9898 provides a STROBE output pulse that can be used to trigger the camera flash circuit. STROBE operation is set by only one register, as described in Table XXV. The STROBE output is held Low when ...
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VARIABLE GAIN AMPLIFIER The VGA provides a gain range dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain needed to match input signal with ...
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AD9898 VDD 1 (INPUT) CLI 2 (INPUT) 1 OUTCONT (INTERNAL SIGNAL) t PWR 4 SERIAL WRITES VD (OUTPUT) HD (OUTPUT) H1, V1, V2, V3, VSG1, VSG2, VSUB, SUBCK, FD DIGITAL OUTPUTS H2, RG, MSHUT, STROBE 2 DCLK2 (OUTPUT) DCLK1 (OUTPUT) ...
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VDD (INPUT) CLI (INPUT) OUTCONT (INTERNAL SIGNAL SERIAL WRITES VD (OUTPUT) HD (OUTPUT) DIGITAL OUTPUTS DCLK1 AND 1 DCLK2 AFESTBY (REGISTER) DIGSTBY (REGISTER) NOTES 1 DCLK2 WILL BE OUTPUT ON FD/DLCK2, PIN 16, PROVIDING REGISTER DCLK2SEL (ADDR 0xD5) ...
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AD9898 VDD (INPUT) CLI (INPUT) OUTCONT (INTERNAL) SERIAL WRITES VD ODD FIELD (OUTPUT) HD (OUTPUT) DIGITAL OUTPUTS DCLK1 DCLK2* AFESTBY (REGISTER) DIGSTBY (REGISTER) *DCLK2 WILL BE OUTPUT ON FD/DLCK2, PIN 16, PROVIDING REGISTER DCLK2SEL (ADDR 0xD5 POWER-DOWN MODE ...
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HORIZONTAL TIMING SEQUENCE EXAMPLE Figure 54 shows a sample CCD layout. The horizontal register contains 28 dummy pixels, which will occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at ...
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AD9898 SEQUENCE 2: VERTICAL OPTICAL BLACK LINES CCDIN OPTICAL BLACK VERTICAL SHIFT SHP SHD CLPOB Figure 56. Horizontal Sequence during Vertical Optical Black Pixels SEQUENCE 3: EFFECTIVE PIXEL LINES CCDIN OPTICAL BLACK VERTICAL SHIFT SHP SHD H1 ...
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CIRCUIT LAYOUT INFORMATION The AD9898 typical circuit connection is shown in Figure 58. The PCB layout is critical to achieving good image quality from the AD9898. All of the supply pins, particularly the AVDD, TCVDD, RGVDD, and HVDD supplies, must ...
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AD9898 PIN 1 INDICATOR 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE OUTLINE DIMENSIONS 48-Lead Lead Frame Chip Scale Package [LFCSP] (CP-48) Dimensions shown in millimeters 7.00 0.60 MAX BSC SQ 0.60 MAX 37 36 6.75 TOP BSC SQ ...