AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 51

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

CIRCUIT LAYOUT INFORMATION
The AD9898 typical circuit connection is shown in Figure 58.
The PCB layout is critical to achieving good image quality from
the AD9898. All of the supply pins, particularly the AVDD,
TCVDD, RGVDD, and HVDD supplies, must be decoupled to
ground with good quality high frequency chip capacitors. The
decoupling capacitors should be located as close as possible to
the supply pins and should have a very low impedance path to a
continuous ground plane. There should also be a 4.7 µF or
larger value bypass capacitor for each main supply—AVDD,
RGVDD, HVDD, and DRVDD—although this is not necessary
for each individual pin. For most applications, it is easier to
share the supply for RGVDD and HVDD, which may be done
as long as the individual supply pins are separately bypassed. A
separate 3 V supply may also be used for DRVDD, but this
REV. 0
SUPPLY
DRIVER
TO MECHANICAL SHUTTER CIRCUIT
3V
EXTERNAL SYNC FROM ASIC/DSP
DCLK1, FD/DCLK2, HD, VD
4.7 F
OUTPUTS
TO STROBE CIRCUIT
DATA
0.1 F
VSUB TO CCD
10
OUTCONT
DRVDD
DRVSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
4
Figure 58. Typical Circuit Configuration
10
11
12
ANALOG SUPPLY
1
2
3
4
5
6
7
8
9
13
0.1 F
48
PIN 1
IDENTIFIER
ANALOG
SUPPLY
14 15 16 17 18 19 20 21 22 23 24
47 46 45 44 43 42 41 40 39 38 37
3V
3V
SUPPLY
DRIVER
(Not to Scale)
AD9898
TOP VIEW
3V
10k
0.1 F
–51–
supply pin should still be decoupled to the same ground plane
as the rest of the chip. A separate ground for DRVSS is not
recommended.
The analog bypass pins (REFB, REFT) also should be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor also should be located
close to the pin.
The H1, H2, and RG traces should be designed to have low
inductance to avoid excessive distortion of the signals. Heavier
traces are recommended because of the CCD’s large transient
current demand on H1 and H2. When possible, physically
locating the AD9898 closer to the CCD will reduce the induc-
tance on these lines. As always, the routing path should be as
direct as possible from the AD9898 to the CCD.
36
35
34
33
32
31
30
29
28
27
26
25
3
SCK
SL
SDATA
REFB
REFT
AVSS
CCDIN
AVDD
CLI
TCVDD
TCVSS
RGVDD
7
H2, H1, RG
1.0 F
1.0 F
0.1 F
0.1 F
V1–V4
VSG1, VSG2
SUBCK
TO V-DRIVER
4.7 F
0.1 F
3
INPUT CLOCK
CCD SIGNAL
3V
ANALOG SUPPLY
SERIAL
INTERFACE
0.1 F
3V
ANALOG SUPPLY
AD9898