AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 40

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9898
VSG TIMING
The VSG timing is controlled using the registers in Table XXIII.
Two unique preprogrammed VSG pulses can be configured
using the VSGTOG1_x (x = 0, 1) registers. As shown in
Figure 42, the period of the VSG pulse is set by programming
the VSGLEN register. The VSGSELx (x = 0, 1) can then be
used to point to either the VSGTOG1_0 or VSGTOG1_1 pulse.
Register
Name
VSGMASK
VSG_EN
VSGTOG1_0
VSGTOG1_1
VSGLEN
VSGSEL0
VSGSEL1
VSGACTLINE
ST COUNTER
Bit
Width
6
1
11
11
8
1
1
7
(FIXED)
13-BIT
VSGx
HD
VD
Register Type
Control (Addr 0x0A)
Control (Addr 0x0B)
Sys_Reg(13)
Sys_Reg(13)
Sys_Reg(14)
Mode_Reg(1)
Mode_Reg(1)
Mode_Reg(1)
1. VSGTOG1_x (x = 0, 1) REFERENCES THE 13-BIT ST COUNTER.
2. VSGACTLINE (PROGRAMMABLE AT MODE_REG (1)).
3. VSGLEN (PROGRAMMABLE AT SYS_REG (14)).
PROGRAMMABLE CLOCK POSITION
VSGTOG1_x (PROGRAMMABLE AT SYS_REG (13)).
0
1
Figure 42. Example of VSG Pulse
VSGACTLINE
Table XXIII. VSG Registers
ST
ST
ST
Reference
Counter
2
–40–
0–8191 Pixels
0–8191 Pixels
0–255 Pixels
High/Low
High/Low
0–128 Lines
Range
High/Low
Figure 42 also shows an example of the VSG pulse being output
in the fourth line by setting the VSGACTLINE = 3. The VSG1
and VSG2 pulses reference the 13-bit fixed ST counter, which
starts counting from the line set in the VSGACTLINE register.
The 13-bit counter allows for overlapping of the VSG pulse into
the next line, if needed.
3
Description
VSG Mask Control
(00 = VSG1 masked, VSG2 masked)
(02 = VSG1 not masked, VSG2 masked)
(08 = VSG1 masked, VSG2 not masked)
(0A = VSG1 not masked, VSG2 not masked)
VSG Output Enable Control
(0 = Disable VSG Outputs,
1 = Enable VSG Outputs)
VSG Sequence 1, Toggle Position 1
VSG Sequence 2, Toggle Position 1
VSG Pulsewidth
VSG1 Output Selector
(0 = VSGTOG1_0 applied on VSG1 output,
1 = VSGTOG1_1 applied on VSG1 output)
VSG2 Output Selector
(0 = VSGTOG1_0 applied on VSG2 output,
1 = VSGTOG1_1 applied on VSG2 output)
VSG Active Line
VSGLEN
1
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