AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 24

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9898
HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING
The HD and VD output pulses are programmable using the
registers listed in Table XI. The HD output is asserted low at
the start of the horizontal line shift. The VD output is asserted
low at the start of each line. As shown in Figure 18, the 11-bit
VD counter is used to count the number of lines set by the
VDLEN register. The 12-bit HD counter is used to count the
number of pixels in each line set by the HDLEN register. For
example, if the CCD array size is 2000 lines by 2100 pixels per
line, VDLEN = 2000 and HDLEN = 0xC28. The HLEN regis-
ter sets the HL counter that is used as a reference for the rising
edge of the HD pulse.
Register
Name
HDLEN
HLEN
HDRISE
HDLASTLEN*
VDLEN
VDRISE
*Register value must be a gray code number. (See Gray Code Registers section.)
GRAY COUNTER
VD COUNTER
HL COUNTER
+ SETUP
12
10
12-BIT
Bit
Width
10
12
11
4
11-BIT
10-BIT
VD
HD
1. THE SETUP DELAY IS 4 CLI CYCLES. THE ACTUAL LENGTH OF ONE LINE IS 4
2. VDRISE REFERENCES THE 11-BIT VD COUNTER.
3. HDRISE REFERENCES THE 10-BIT HL COUNTER.
PROGRAMMABLE CLOCK POSITIONS
1. HDRISE (SYS_REG(16))
2. VDRISE (SYS_REG(16))
MORE CYCLES THAN THE VALUE SET IN HDLEN AND HDLASTLEN DUE TO SETUP DELAY.
HLEN
1
LINE LENGTH =
Register Type
Sys_Reg(12)
Sys_Reg(12)
Sys_Reg(16)
Mode_Reg(1)
Mode_Reg(1)
Sys_Reg(16)
HDLEN
HDLEN + 4
000
Figure 18. VD and HD Horizontal Timing
Table XI. HD and VD Registers
SETUP
Reference
HL
HD
VD
Counter
001
–24–
Special Note about the HDLEN Register
The 12-bit HD counter value must be programmed using a gray
code number. There is also a 4-clock cycle setup period that
must be considered when determining the HDLEN register
value, as shown in Figure 18. As a result of the 4-clock cycle
setup period, the value of HDLEN is always equal to the actual
number of pixels per line minus four. For example, if there are
2100 pixels per line, HDLEN equals (2100 – 4) = 2096. The
gray code value of 2096 is 0xC28, which is what would be pro-
grammed in the HDLEN register.
VDLEN
2
0–4095 Pixels
0–1023 Pixels
0–1023 Pixels
0–4095 Pixels
0–2047 Lines
0–15 Lines
Range
002
Description
12-Bit Gray Code Counter Value
10-Bit HL Counter Value
HD Rise Position
HD Last Line Length
VD Counter Value
VD Rise Position
HDLASTLEN
N
2048
REV. 0